Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment

SUMMARY Dynamically-programmable gate arrays (DPGAs) pro-mise lower-cost implementations than conventional field-programmablegate arrays (FPGAs) since they efficiently reuse limited hardware resourcesin time. One of the typical DPGA architectures is a multi-context FPGA(MC-FPGA) that requires multiple memory bits per configuration bit to re-alize fast context switching. However, this additional memory bits causesignificant overhead in area and power consumption. This paper presentsnovel architecture of a switch element to overcome the required capacityof configuration memory. Our main idea is to exploit redundancy betweendifferent contexts by using a fine-grained switch element. The proposedMC-FPGA is designed in a 0.18 µm CMOS technology. Its maximumclock frequency and the context switching frequency are measured to be310MHz and 272MHz, respectively. Moreover, novel CAD process thatexploits the redundancy in configuration data, is proposed to support theMC-FPGA architecture. key words: dynamically-programmable gate array, multi-context FPGA,configuration data redundancy