Vector Computer Architecture and Processing Techniques

Publisher Summary Vector- or array-processing computers are essentially designed to maximize the concurrent activities inside a computer and to match the bandwidth of data flow to the execution speed of various subsystems within a computer. This chapter reviews architectural advances in vector-processing computers. It describes the two major classes of vector machines—namely, the pipeline computers and array processors. Problems associated with designing pipeline computers are also presented with examples from the Texas Instruments Advanced Scientific Computer (TI-ASC), Control Data STring ARay (STAR-100) and CYBER-205 Computers, Cray Research CRAY-1, and Floating-Point Systems AP-120B. The chapter describes the architectures of recently developed SIMD array processors. Further, it examines the development experiences of the Burroughs Scientific Processor (BSP) and the Goodyear Aerospace Massively Parallel Processor (MPP). Recent research works on array and pipeline processors are also summarized. The chapter concludes with the evaluation of the performance of pipeline and array processors and explores various optimization techniques for vector operations. Hardware, software, and algorithmic issues of vector-processing systems and future trends of vector computers are also discussed.

[1]  Janak H. Patel.  Pipelines with internal buffers , 1978, ISCA '78.

[2]  Kenneth E. Batcher,et al.  Design of a Massively Parallel Processor , 1980, IEEE Transactions on Computers.

[3]  G. Jack Lipovski,et al.  Switched multiple instruction, multiple data stream processing , 1974, ISCA '75.

[4]  Howard Jay Siegel,et al.  A Model of SIMD Machines and a Comparison of Various Interconnection Networks , 1979, IEEE Transactions on Computers.

[5]  Edward W. Kozdrowicki,et al.  Second Generation of Vector Supercomputers , 1980, Computer.

[6]  Tse-Yun Feng.  Data Manipulating Functions in Parallel Processors and Their Implementations , 1974, IEEE Transactions on Computers.

[7]  David B. Loveman,et al.  Program Improvement by Source-to-Source Transformation , 1977, J. ACM.

[8]  Jean-Loup Baer,et al.  Computer systems architecture , 1980 .

[9]  Edward S. Davidson,et al.  A multiminiprocessor system implemented through pipelining , 1974, Computer.

[10]  M. T. Kaufman,et al.  An Almost-Optimal Algorithm for the Assembly Line Scheduling Problem , 1974, IEEE Transactions on Computers.

[11]  Duncan H. Lawrie,et al.  High Speed Computer and Algorithm Organization , 1977 .

[12]  David A. Padua,et al.  High-Speed Multiprocessors and Compilation Techniques , 1980, IEEE Transactions on Computers.

[13]  D. N. Senzig,et al.  Computer organization for array processing , 1965, AFIPS '65 (Fall, part I).

[14]  Richard M. Russell,et al.  The CRAY-1 computer system , 1978, CACM.

[15]  David L. Kuck,et al.  The Structure of Computers and Computations , 1978 .

[16]  Jacob T. Schwartz,et al.  Optimization of Very High Level Languages - I. Value Transmission and Its Corollaries , 1975, Comput. Lang..

[17]  Faye A. Briggs.  Performance of memory configurations for parallel-pipelined computers , 1978, ISCA '78.

[18]  S. F. Anderson,et al.  The IBM system/360 model 91: floating-point execution unit , 1967 .

[19]  Mary Jane Irwin,et al.  On-line algorithms for the design of pipeline architectures , 1979, ISCA '79.

[20]  C. V. Ramamoorthy,et al.  Efficiency in generalized pipeline networks , 1974, AFIPS '74.

[21]  Tse-Yun Feng,et al.  On a Class of Multistage Interconnection Networks , 1980, IEEE Transactions on Computers.

[22]  Marshall C. Pease,et al.  The Indirect Binary n-Cube Microprocessor Array , 1977, IEEE Transactions on Computers.

[23]  Kai Hwang,et al.  Resource Optimization of a Parallel Computer for Multiple Vector Processing , 1980, IEEE Transactions on Computers.

[24]  Dhiraj K. Pradhan,et al.  A Uniform Representation of Single-and Multistage Interconnection Networks Used in SIMD Machines , 1980, IEEE Transactions on Computers.

[25]  John P. Hayes,et al.  Computer Architecture and Organization , 1980 .

[26]  Janak H. Patel,et al.  Processor-memory interconnections for multiprocessors , 1979, ISCA '79.

[27]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.

[28]  Richard G. Cooper.  The Distributed Pipeline , 1977, IEEE Transactions on Computers.

[29]  Mary Jane Irwin.  A pipelined processing unit for on-line division , 1978, ISCA '78.

[30]  Tilak Agerwala,et al.  A modeling approach and design tool for pipelined central processors , 1979, ISCA '79.

[31]  R. M. Tomasulo,et al.  An efficient algorithm for exploiting multiple arithmetic units , 1995 .

[32]  Alexander Thomasian,et al.  A design study of a shared resource computing system , 1976, ISCA.

[33]  David J. Kuck,et al.  A Survey of Parallel Machine Organization and Programming , 1977, CSUR.

[34]  Jayanti C. Majithia.  Some Comments Concerning Design of Pipeline Arithmetic Arrays , 1976, IEEE Trans. Computers.

[35]  J. E. Thornton.  Design of a Computer: The Control Data 6600 , 1970 .

[36]  Kai Hwang.  Global and Modular Two's Complement Cellular Array Multipliers , 1979, IEEE Trans. Computers.

[37]  H. T. Kung,et al.  Systolic Arrays for (VLSI). , 1978 .

[38]  Harold S. Stone.  Introduction to Computer Architecture , 1980 .

[39]  Kenneth J. Thurber.  Large scale computer architecture: Parallel and associative processors , 1976 .

[40]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[41]  Michael J. Flynn,et al.  Some Computer Organizations and Their Effectiveness , 1972, IEEE Transactions on Computers.

[42]  FAYÉ A. BRIGGS,et al.  PM4—A reconfigurable multiprocessor system for pattern recognition and image processing , 1979, 1979 International Workshop on Managing Requirements Knowledge (MARK).

[43]  Roland N. Ibbett.  The MU5 instruction pipeline , 1972, Comput. J..

[44]  Richard M. Brown,et al.  The ILLIAC IV Computer , 1968, IEEE Transactions on Computers.

[45]  Kai Hwang,et al.  Performance evaluation and resource optimization of multiple SIMD computer organizations , 1979 .

[46]  Sheldon S. L. Chang.  Multiple-Read Single-Write Memory and Its Applications , 1980, IEEE Transactions on Computers.

[47]  C. V. Ramamoorthy,et al.  Pipeline Architecture , 1977, CSUR.

[48]  Arvid Gunnar Larson.  Cost-effective processor design with an application to fast fourier transform computers. , 1973 .

[49]  Gary J. Nutt.  Memory and Bus Conflict in an Array Processor , 1977, IEEE Transactions on Computers.

[50]  Sartaj Sahni,et al.  Data broadcasting in SIMD computers , 1981, IEEE Transactions on Computers.

[51]  David J. Kuck.  ILLIAC IV Software and Application Programming , 1968, IEEE Transactions on Computers.

[52]  Harold S. Stone.  Sorting on STAR , 1978, IEEE Transactions on Software Engineering.

[53]  R. Bernhard.  Computers. II. Minis and mainframes , 1981, IEEE Spectrum.

[54]  Ahmed Sameh,et al.  The Illiac IV system , 1972 .

[55]  Edward S. Davidson,et al.  Organization of Semiconductor Memories for Parallel-Pipelined Processors , 1977, IEEE Transactions on Computers.

[56]  Harold S. Stone,et al.  Parallel Processing with the Perfect Shuffle , 1971, IEEE Transactions on Computers.

[57]  Sudhir Ahuja,et al.  Effective Pipelining of Digital Systems , 1978, IEEE Transactions on Computers.

[58]  C. V. Ramamoorthy,et al.  Pipelining: the generalized concept and sequencing strategies , 1974, AFIPS '74.

[59]  Richard L. Sites.  An analysis of the Cray-1 computer , 1978, ISCA '78.

[60]  Kai Hwang,et al.  Performance Modeling of Shared-Resource Array Processors , 1981, IEEE Transactions on Software Engineering.

[61]  Svetlana P. Kartashev,et al.  Problems of Designing Supersystems with Dynamic Architectures , 1980, IEEE Transactions on Computers.

[62]  Kenneth E. Batcher.  STARAN parallel processor system hardware , 1974, AFIPS '74.

[63]  Charles Purcell.  The control data STAR-100: performance measurements , 1974, AFIPS '74.

[64]  Michael J. Flynn,et al.  Pipelining of Arithmetic Functions , 1972, IEEE Trans. Computers.

[65]  Robert P. Roesser.  Two-Dimensional Microprocessor Pipelines for Image Processing , 1978, IEEE Transactions on Computers.

[66]  Duncan H. Lawrie,et al.  The Prime Memory System for Array Access , 1982, IEEE Transactions on Computers.

[67]  Alumkal Thampy Thomas.  Scheduling of multiconfigurable pipelines , 1977 .

[68]  Kenneth E. Batcher.  The Multidimensional Access Memory in STARAN , 1977, IEEE Transactions on Computers.