FPGA-based MPEG2 decoder

This paper describes the design and implementation of a full custom, FPGA-based MPEG2 decoder. This FPGA design is attractive for its inherent In Circuit Configurability (ICR) and In Circuit programmability (ISP) capabilities. As such, this design is suitable for low cost, multi-standard, standard video decoders.

[1]  Joan L. Mitchell,et al.  MPEG Video: Compression Standard , 1996 .

[2]  Peter Pirsch,et al.  VLSI architectures for video compression , 1995, Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics.

[3]  H. I. Helal,et al.  Efficient realization of FPGA-based two dimensional discrete cosine transform , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[4]  Peter Pirsch,et al.  VLSI architectures for video compression-a survey , 1995, Proc. IEEE.