A single-channel 10b 1GS/s ADC with 1-cycle latency using pipelined cascaded folding

A 10b 1 GS/s ADC employing a single channel cascaded folding architecture is presented. Conversion speed of 1 GS/s is attained by incorporating low-power distributed track-and-hold amplifiers after each folder. This ADC achieves a record 55.6 dB peak SNDR and a 64 dB peak SFDR and sustains a latency of one clock cycle. DNL and INL at 1 GS/s sampling rate are measured 0.4 LSB and 1.1 LSB. Fabricated in a 0.35 mum BiCMOS process, the ADC consumes 2 W from a 3.5 V supply.

[1]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  M. Vertregt,et al.  A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[3]  Jingbo Wang,et al.  A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture , 2006, IEEE Journal of Solid-State Circuits.

[4]  Jingbo Wang,et al.  A 1GS/s 11b Time-Interleaved ADC in 0.13/spl mu/m CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[5]  Raf Roovers,et al.  12-B, 60-MSample/S cascaded folding and interpolating ADC , 1999 .

[6]  Mau-Chung Frank Chang,et al.  A 10-b, 1-GSample/s track-and-hold amplifier using SiGe BiCMOS technology , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[7]  R. Roovers,et al.  A 12 b 50 M sample/s cascaded folding and interpolating ADC , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[8]  Myung-Jun Choe,et al.  An 8 b 100 MSample/s CMOS pipelined folding ADC , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).