VHDL fault simulation for defect-oriented test and diagnosis of digital ICs

For high quality VLSI products, exhibiting very low escape rates, defect-oriented testing becomes mandatory. The design activity is more and more supported by hardware description languages, like VHDL; hence, the testing activity needs to follow this trend. In this paper, a VHDL-based methodology for test preparation of digital ICs is proposed and a new set of tools for defect-oriented VHDL fault simulation are presented, using a commercial VHDL simulator. The proposed methodology is also shown to be effective in supporting realistic fault diagnosis. Simulation results for benchmark circuits are presented.

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