Random pattern testable logic synthesis

Previous procedures for synthesis of testable logic guarantee that all faults in the synthesized circuits are detectable. However, the detectability of many faults in these circuits can be very low leading to poor random pattern testability. A new procedure to perform logic synthesis that synthesizes random pattern testable multilevel circuits is proposed. Experimental results show that the circuits synthesized by the proposed procedure tstfx are significantly more random pattern testable and smaller than those synthesized using its counterpart fast_extract (fx) in SIS. The proposed synthesis procedure design circuits that require only simple random pattern generators in built-in self-test, thereby obviating the need for complex BIST circuitry.

[1]  Daniel Brand.  Redundancy and Don't Cares in Logic Synthesis , 1983, IEEE Transactions on Computers.

[2]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[3]  Prithviraj Banerjee,et al.  Logic Partitioning and Resynthesis for Testability , 1991, 1991, Proceedings. International Test Conference.

[4]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[5]  Amitava Majumdar,et al.  On the distribution of fault coverage and test length in random testing of combinational circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[6]  Nur A. Touba,et al.  Automated logic synthesis of random pattern testable circuits , 1994, Proceedings., International Test Conference.

[7]  Kurt Keutzer,et al.  On properties of algebraic transformation and the multifault testability of multilevel logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Janusz Rajski,et al.  The testability-preserving concurrent decomposition and factorization of Boolean expressions , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Hamid Savoj,et al.  Don't cares in multi-level network optimization , 1992 .

[10]  Andrzej Krasniewski,et al.  Random testability of redundant circuits , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[11]  R. Dandapani,et al.  On the Design of Logic Networks with Redundancy and Testability Considerations , 1974, IEEE Transactions on Computers.

[12]  Jacob Savir,et al.  On Random Pattern Test Length , 1984, IEEE Transactions on Computers.

[13]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Andrzej Krasniewski.  CAN REDUNDANCY ENHANCE TESTABILITY? , 1991, 1991, Proceedings. International Test Conference.

[15]  Edward J. McCluskey,et al.  Pseudorandom Testing , 1987, IEEE Transactions on Computers.

[16]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Chen-Huan Chiang,et al.  Random Pattern Testable Logic Synthesis , 1994, IEEE/ACM International Conference on Computer-Aided Design.