A Survey of Yield Modeling and Yield Enhancement Methods

Fast yield learning is critical to bringing products to the market in a timely fashion and is strongly linked to product revenues. This paper reviews methods to enable efficient yield learning, focusing on methods to quantify the most significant yield detractors and on in-line excursion detection methodologies.

[1]  Jiann-Liang Chen,et al.  Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Rob A. Rutenbar,et al.  Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Greg Yeric,et al.  Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below , 2005, IEEE Design & Test of Computers.

[4]  C. Terwiesch,et al.  The economics of yield-driven processes , 1999 .

[5]  Anjali Kinra,et al.  Logic mapping on a microprocessor , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[6]  J. S. Hunter,et al.  Statistics for Experimenters: An Introduction to Design, Data Analysis, and Model Building. , 1979 .

[7]  H. Masuda,et al.  Development of a large-scale TEG for evaluation and analysis of yield and variation , 2004, IEEE Transactions on Semiconductor Manufacturing.

[8]  Wojciech Maly,et al.  Improved yield model for submicron domain , 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[9]  R. D. Blanton,et al.  Benchmarking diagnosis algorithms with a diverse set of IC deformations , 2004 .

[10]  NaikSamir,et al.  Failure Analysis of High-Density CMOS SRAMs , 1993 .

[11]  Linda S. Milor,et al.  Backend dielectric breakdown dependence on linewidth and pattern density , 2007, Microelectron. Reliab..

[12]  P.R. Chidambaram,et al.  Pattern Based Prediction for Plasma Etch , 2007, IEEE Transactions on Semiconductor Manufacturing.

[13]  Sandeep Kumar Goel,et al.  Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study , 2009, 2009 27th IEEE VLSI Test Symposium.

[14]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[15]  Hans-Joachim Wunderlich,et al.  An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy , 2007, 12th IEEE European Test Symposium (ETS'07).

[16]  J. Li,et al.  Construction of a "Grand Pareto" for line yield loss, by process loop using limited data sets , 1997, 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop ASMC 97 Proceedings.

[17]  Virginia F. Flack.  Introducing dependency into IC yield models , 1985 .

[18]  Timothy A. Brunner,et al.  Impact of lens aberrations on optical lithography , 1997, IBM J. Res. Dev..

[19]  Andrzej J. Strojwas,et al.  Effective excursion detection by defect type grouping in in-line inspection and classification , 1999 .

[20]  J. Segal,et al.  Critical area based yield modeling on an advanced microprocessor design , 2000, Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130).

[21]  Costas J. Spanos,et al.  Optimum sampling for characterization of systematic variation in photolithography , 2002, SPIE Advanced Lithography.

[22]  Janusz Rajski,et al.  A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis , 2006, 2006 IEEE International Test Conference.

[23]  Xiao-Yu Li,et al.  FPGA as Process Monitor-an effective method to characterize poly gate CD variation and its impact on product performance and yield , 2004, IEEE Transactions on Semiconductor Manufacturing.

[24]  Jin-Fu Li,et al.  Memory Built-in Self-Repair Planning Framework for RAMs in SoCs , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Jin-Fu Li,et al.  ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Linda S. Milor,et al.  Analysis of the layout impact on electric fields in interconnect structures using finite element method , 2004, Microelectron. Reliab..

[27]  Hajime Aoyama,et al.  Correction for local flare effects approximated with double Gaussian profile in ArF lithography , 2003 .

[28]  Chenming Hu,et al.  Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction , 2004, IEEE Transactions on Semiconductor Manufacturing.

[29]  Scott MacKinnon,et al.  Statistical methods for visual defect metrology , 1998 .

[30]  Wojciech Maly,et al.  New yield models for DSM manufacturing , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[31]  Costas J. Spanos,et al.  Fundamentals of Semiconductor Manufacturing and Process Control: May/Fundamentals of Semiconductor Manufacturing and Process Control , 2006 .

[32]  D. Farrington,et al.  In-line SEM based ADC for advanced process control , 2000, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072).

[33]  Kenneth M. Butler,et al.  Correlation of logical failures to a suspect process step , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[34]  Rajiv V. Joshi,et al.  Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[35]  Chenming Hu,et al.  Intra-field gate CD variability and its impact on circuit performance , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[36]  D. Boning,et al.  Integrated chip-scale simulation of pattern dependencies in copper electroplating and copper chemical mechanical polishing processes , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

[37]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[38]  R. E. Langford,et al.  The application and validation of a new robust windowing method for the Poisson yield model , 2001, 2001 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (IEEE Cat. No.01CH37160).

[39]  Wojciech Maly,et al.  Yield-oriented computer-aided defect diagnosis , 1995 .

[40]  L. Milor,et al.  Performance modeling using additive regression splines , 1995 .

[41]  Douglas C. Montgomery,et al.  Statistical Quality Control , 2008 .

[42]  Wojciech Maly,et al.  Failure analysis of high-density CMOS SRAMs: using realistic defect modeling and I/sub DDQ/ testing , 1993, IEEE Design & Test of Computers.

[43]  A. J. Strojwas,et al.  Test structures based VLSIC yield ramp maximization , 2001, 2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443).

[44]  D. M. H. Walker,et al.  VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[45]  A. Skumanich,et al.  Advanced process development and control based on a fully automated SEM with ADC , 1999, 10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295).

[46]  W. Kent Fuchs,et al.  Efficient Spare Allocation in Reconfigurable Arrays , 1986, 23rd ACM/IEEE Design Automation Conference.

[47]  Vijayan N. Nair,et al.  Model-free estimation of defect clustering in integrated circuit fabrication , 1997 .

[48]  Shyue-Kung Lu,et al.  Efficient BISR Techniques for Embedded Memories Considering Cluster Faults , 2010, 13th Pacific Rim International Symposium on Dependable Computing (PRDC 2007).

[49]  Wu-Tung Cheng,et al.  Compression mode diagnosis enables high volume monitoring diagnosis flow , 2005, IEEE International Conference on Test, 2005..

[50]  S. C. Abraham.  A new chemistry for a high-density plasma etcher that improves etch rate loading on the TiN ARC layer when geometries are below 0.5 micron , 1996, IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings.

[51]  S. Sekiyama,et al.  Possibilities and limitation of SiO/sub 2/ etching with parallel plate RF plasma , 1995, Proceedings of International Symposium on Semiconductor Manufacturing.

[52]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[53]  C. Stapper.  Correlation analysis of particle clusters on integrated circuit wafers , 1987 .

[54]  G. Yeric,et al.  Infrastructure for successful BEOL characterization and yield ramp at the 65 nm node and below , 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

[55]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[56]  Jin-Fu Li,et al.  Raisin: Redundancy Analysis Algorithm Simulation , 2007, IEEE Design & Test of Computers.

[57]  L. Milor,et al.  Determining the Impact of Within-Die Variation on Circuit Timing , 2011, IEEE Transactions on Semiconductor Manufacturing.

[58]  K. Imai,et al.  A novel filtering method to extract three critical yield loss components (gross, repeated, and random) FIMER , 2000 .

[59]  Fook-Luen Heng,et al.  Backend CAD flows for "restrictive design rules" , 2004, ICCAD 2004.

[60]  K. Ronse,et al.  Optical Lithography Techniques for 0.25 μm and Below , 1994, ESSDERC '94: 24th European Solid State Device Research Conference.

[61]  Wojciech Maly,et al.  Extraction of Defect Density and Size Distributions from Wafer Sort Test Results , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[62]  Timothy N. Trick,et al.  A Study of Variance Reduction Techniques for Estimating Circuit Yields , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[63]  Anthony J. Walton,et al.  Automatic in-line to end-of-line defect correlation using FSRAM test structure for quick killer defect identification , 1994, Proceedings of 1994 IEEE International Conference on Microelectronic Test Structures.

[64]  J. Pineda de Gyvez,et al.  Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits , 2004, IEEE Journal of Solid-State Circuits.

[65]  Harry J. Levinson,et al.  Principles of Lithography , 2001 .

[66]  Nam Sung Kim,et al.  Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC , 2010, 2010 IEEE International Conference on Computer Design.

[67]  W. Kent Fuchs,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987 .

[68]  Kurt G. Ronse,et al.  Influence of gate patterning on line edge roughness , 2003 .

[69]  Wojciech Maly,et al.  Yield estimation model for VLSI artwork evaluation , 1983 .

[70]  R. Leachman,et al.  Integration of speed economics into decision-making for manufacturing management , 2007 .

[71]  Y. Yeo,et al.  Process-strained Si (PSS) CMOS technology featuring 3D strain engineering , 2003, IEEE International Electron Devices Meeting 2003.

[72]  C. H. Stapper,et al.  Integrated circuit yield management and yield analysis: development and implementation" ieee trans , 1995 .

[73]  Seong-Woon Choi,et al.  Measurement of the flare and in-field linewidth variation due to the flare , 2002, SPIE Advanced Lithography.

[74]  S.W. Director,et al.  An efficient methodology for building macromodels of IC fabrication processes , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[75]  Wojciech Maly,et al.  Analysis of the impact of proximity correction algorithms on circuit performance , 1999 .

[76]  Sung-Mo Kang,et al.  Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[77]  Erik Jan Marinissen,et al.  Yield analysis for repairable embedded memories , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

[78]  Cheryl Gaimon,et al.  Improving Manufacturing Performance Through Process Change and Knowledge Creation , 2000 .

[79]  L. Milor,et al.  Yield modeling based on in-line scanner defect sizing and a circuit's critical area , 1999 .

[80]  M. E. Thomas,et al.  Extraction of defect size distributions in an IC layer using test structure data , 1994 .

[81]  A. Misaka,et al.  A simulation of micro-loading phenomena in dry-etching process using a new adsorption model , 1993, Proceedings of IEEE International Electron Devices Meeting.

[82]  Hung-Jen Lin,et al.  Optimal testing of VLSI analog circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[83]  Ram Akella,et al.  In-line defect sampling methodology in yield management: an integrated framework , 1996 .

[84]  Young-Jun Kwon,et al.  Yield learning via functional test data , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[85]  Charles Weber.  Yield learning and the sources of profitability in semiconductor manufacturing and process development , 2002, 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259).

[86]  M.A. Merino,et al.  SmartBit/sup TM/: bitmap to defect correlation software for yield improvement , 2000, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072).

[87]  Manish Sharma,et al.  Determination of Dominant-Yield-Loss Mechanism with Volume Diagnosis , 2010, IEEE Design & Test of Computers.

[88]  J.D. Hibbeler,et al.  Measurement and reduction of critical area using Voronoi diagrams , 2005, IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005..

[89]  Wojciech Maly,et al.  A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[90]  C. Terwiesch,et al.  Learning and process improvement during production ramp-up , 1998 .

[91]  Wu-Tung Cheng,et al.  Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data , 2008, 2008 IEEE International Test Conference.

[92]  Janusz Rajski,et al.  Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement , 2007, 12th IEEE European Test Symposium (ETS'07).

[93]  Allan Y. Wong.  A statistical approach to identify semiconductor process equipment related yield problems , 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[94]  A. Blauberg,et al.  The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in Volume Semiconductor Manufacturing , 2007, IEEE Transactions on Semiconductor Manufacturing.

[95]  Yeng Peng,et al.  Layer yield estimation based on critical area and electrical defect monitor data , 1999, 1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No.99CH36314).

[96]  Andrzej J. Strojwas,et al.  Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[97]  Noel A Cressie,et al.  Statistics for Spatial Data. , 1992 .

[98]  Feng Wang,et al.  An effective method of characterization poly gate CD variation and its impact on product performance and yield , 2003 .

[99]  D. Boning,et al.  MODELING OF PATTERN DEPENDENCIES IN ABRASIVE-FREE COPPER CHEMICAL MECHANICAL POLISHING PROCESSES , 2001 .

[100]  Jayanthi Pallinti,et al.  Electrical characterization of the copper CMP process and derivation of metal layout rules , 2003 .

[101]  I. Kurachi,et al.  New Mechanism of LER Formation in Gate Process , 2006, 2006 IEEE International Symposium on Semiconductor Manufacturing.

[102]  D. K. de Vries,et al.  Methods to quantify the detection probability of killing defects , 2005 .

[103]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[104]  O. S. Nakagawa,et al.  Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing , 1998 .

[105]  Yi Xu,et al.  The copy-exactly ramp-up strategy: trading-off learning with process change , 2004, IEEE Transactions on Engineering Management.

[106]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .

[107]  Sunnys Hsieh,et al.  The short-loop process tuning & yield evaluation by using the addressable failure site test structures (AFS-TS) , 2000, Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130).

[108]  Jin-Fu Li,et al.  ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[109]  R. Wise,et al.  Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing , 2006, IEEE Transactions on Electron Devices.

[110]  L. Milor,et al.  An analytical model of multiple ILD thickness variation induced by interaction of layout pattern and CMP process , 2000 .

[111]  D. M. H. Walker,et al.  Improvement of SRAM-based failure analysis using calibrated Iddq testing , 1996, Proceedings of 14th VLSI Test Symposium.

[112]  R.L. Guldi,et al.  In-line defect reduction from a historical perspective and its implications for future integrated circuit manufacturing , 2004, IEEE Transactions on Semiconductor Manufacturing.

[113]  Alberto L. Sangiovanni-Vincentelli,et al.  Computing parametric yield accurately and efficiently , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[114]  P. Stolk,et al.  Impact of ion implantation statistics on V/sub T/ fluctuations in MOSFETs: comparison between decaborane and boron channel implants , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[115]  Chris A. Mack.  Measuring and modeling flare in optical lithography , 2003, SPIE Advanced Lithography.

[116]  Sungho Kang,et al.  A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[117]  P.A.J. Volf,et al.  Simplified implementation of the windowing method for systematic and random yield calculation , 2004, IEEE Transactions on Semiconductor Manufacturing.

[118]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[119]  Janusz Rajski,et al.  Diagnosis of Failing Scan Cells through Orthogonal Response Compaction , 2010, 2011 Sixteenth IEEE European Test Symposium.

[120]  Sani R. Nassif,et al.  A Methodology for Worst-Case Analysis of Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[121]  Wojciech Maly,et al.  Computer-aided design for VLSI circuit manufacturability , 1990, Proc. IEEE.