Linearly graded doping drift region: A novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances

A linearly graded doping drift region structure, a novel lateral voltage-sustained layer used for improvement of reduced surface field (RESURF) LDMOS transistor performance has been evaluated theoretically, numerically and experimentally in this paper for the first time. Due to the coupling effect of the two-dimensional (2D) electrical field, it is found from the theory developed here that the linearly graded drift region-doped profile can provide a high breakdown voltage while maintaining a high doping dose in the total drift region for minimizing the on-resistance Ron. The characteristics of such an LDMOS have been demonstrated by the 2D semiconductor device simulator MEDICI and further verified by our experimental results. We have obtained a reduction of the on-resistance of 50% from 10.3 mΩ cm2 to 5 mΩ cm2 in the on-state, and an increase of the breakdown voltage by a factor of 2.5 from 90 V to 234 V in the off-state, compared to the values for conventional RESURF devices. The experimental results verify the performance improvement predicted by the simulation and theory.

[1]  S. Merchant,et al.  Analytical model for the electric field distribution in SOI RESURF and TMBS structures , 1999 .

[2]  Shengdong Zhang,et al.  Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices , 1999 .

[3]  G. F. Niu,et al.  Comparisons and extension of recent surface potential models for fully depleted short-channel SOI MOSFET's , 1996 .

[4]  Jin-Hau Kuo,et al.  Deep submicrometer double-gate fully-depleted SOI PMOS devices: a concise short-channel effect threshold voltage model using a quasi-2D approach , 1996 .

[5]  K. Board,et al.  Lateral high-voltage devices using an optimized variational lateral doping , 1996 .

[6]  Man Wong,et al.  Implemention of linear doping profiles for high voltage thin-film SOI devices , 1995, Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95.

[7]  Theodore Letavic,et al.  Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors , 1993, [1993] Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs.

[8]  Akio Nakagawa,et al.  Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film , 1991 .

[9]  S. Mukherjee,et al.  Realization of high breakdown voltage (>700 V) in thin SOI devices , 1991, [1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs.

[10]  C.A.T. Salama,et al.  Optimization of RESURF LDMOS transistors: an analytical approach , 1990 .

[11]  H. J. Schulze,et al.  Realization of a high-voltage planar junction termination for power devices , 1989 .

[12]  X.B. Chen,et al.  Optimization of the drift region of power MOSFET's with lateral structures and deep junctions , 1987, IEEE Transactions on Electron Devices.

[13]  V.A.K. Temple,et al.  Multiple-zone single-mask junction termination extension—A high-yield near-ideal breakdown voltage technology , 1987, IEEE Transactions on Electron Devices.

[14]  C. Salama,et al.  High-voltage multiple-resistivity drift-region LDMOS , 1986 .

[15]  S. Colak,et al.  Effects of drift region parameters on the static properties of power LDMOST , 1981, IEEE Transactions on Electron Devices.

[16]  G. Gibbons,et al.  Effect of junction curvature on breakdown voltage in semiconductors , 1966 .

[17]  S. Luryi.  Correction to multiple-zone single-mask junction termination extension ― A high-yield near-ideal breakdown voltage technology , 1988 .

[18]  U. Gosele,et al.  Variation of lateral doping—A new concept to avoid high voltage breakdown of planar junctions , 1985, 1985 International Electron Devices Meeting.

[19]  E.J. Wildi,et al.  Modeling and process implementation of implanted RESURF type devices , 1982, 1982 International Electron Devices Meeting.

[20]  J. Appels,et al.  High voltage thin layer devices (RESURF devices) , 1979, 1979 International Electron Devices Meeting.

[21]  W. Fulop,et al.  Calculation of avalanche breakdown voltages of silicon p-n junctions , 1967 .