An energy recovery D flip-flop for low power semi-custom ASIC design

A sense amplifier D flip-flop with reset function using energy recovery technique, SAERDR (Sense Amplifier Energy Recovery D Flip-flop with Reset Function), is presented. The proposed flip-flop operates with a single phase sinusoidal clock to recover the energy of the clock pin. Simulation results show that the power consumption of clock pin is saving 72% on average as compared to the same implementation using the square-wave clocking scheme for clock frequencies ranging from 10MHz to 60MHz. We also propose a methodology to design a semi-custom energy recovery ASIC using SAERDR. In the SMIC 0.13μm CMOS process, a numerical controlled oscillator using our methodology is implemented. Test results show the total power saving is up to 34.9% as compared to the implementation using the conventional D flip-flops MSD (Master Salve D Flip-flop) at 60MHz.

[1]  Vojin G. Oklobdzija,et al.  Clocked CMOS adiabatic logic with integrated single-phase power-clock supply , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Suhwan Kim,et al.  Charge-recovery computing on silicon , 2005, IEEE Transactions on Computers.

[3]  Li Xiao Design of Low Voltage Charge-Recovery Logic Circuit , 2001 .

[4]  Kaushik Roy,et al.  Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.

[6]  Qi Feng The implementation of NCO based on CORDIC algorithm , 2007 .

[7]  Yu Jun-jun Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM , 2006 .

[8]  A. Kramer,et al.  Adiabatic Computing with the 2n-2n2d Logic Family , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[9]  A. Al-Khalili,et al.  Power reduction in energy recovery and square-wave clock distribution networks operating at half frequency with dual-edge triggered flip-flops , 2008, 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference.

[10]  Marios C. Papaefthymiou,et al.  Energy recovering ASIC design , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[11]  V.S. Sathe,et al.  Energy-Efficient GHz-Class Charge-Recovery Logic , 2007, IEEE Journal of Solid-State Circuits.

[12]  Deog-Kyoon Jeong,et al.  An efficient charge recovery logic circuit , 1996, IEEE J. Solid State Circuits.