Integrating Simulation Capabilities in SysML using DEVS

SysML is considered as an emerging standard for system engineering. Using SysML, the system engineer may study alternative system configurations. However, in order to be able to argue for or against a certain configuration, performance evaluation should be performed and SysML models should become executable using a simulation environment. For the simulation community, DEVS formalism provides a conceptual framework for specifying discrete event simulation models in a modular and hierarchical form. In addition DEVS is supported by a wide variety of DEVS simulators built in numerous programming environments. This paper illustrates and exploits the similarities between SysML and DEVS conceptual model and proposes a DEVS profile for SysML to make SysML models executable using a DEVS simulator. Integrating simulation capabilities into SysML models, automatic code generation for DEVS simulators may be possible, facilitating simulation for models already defined in SysML.