A 1.2-V 100KS/S energy efficient supply boosted SAR ADC

This paper presents a new energy efficient supply boosted (SB) successive approximation register (SAR) type analog-to-digital converter (ADC) designed in a high-Vth CMOS process. Supply boosting technique (SBT) improves input common mode range and minimum operation voltage of mixed-signal circuits even when threshold voltages are in the order of the supply voltage. A 10-bit SB- SAR ADC was designed and fabricated in a standard 0.5 μm, 5V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are +0.8V and -0.9V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.24, power consumption of 6μW from a 1.2Volt supply. Measured figure of merit (FoM) was 163fJ and 196fJ per conversion-step for sampling rates of 80KS/s and 100KS/s, respectively.

[1]  Suat U. Ay.  A 1.32pW/frame•pixel 1.2V CMOS energy-harvesting and imaging (EHI) APS imager , 2011, 2011 IEEE International Solid-State Circuits Conference.

[2]  E.C. Dijkmans,et al.  A -90 dB THD rail-to-rail input opamp using a new local charge pump in CMOS , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[3]  R. Castello,et al.  A 1 V 1.8 MHz CMOS switched-opamp SC filter with rail-to-rail output swing , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[4]  Suat U. Ay,et al.  Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[5]  Yngvar Berg,et al.  Ultra low-voltage/low-power digital floating-gate circuits , 1999 .

[6]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[7]  Gabriel A. Rincon-Mora,et al.  Designing 1-V op amps using standard digital CMOS technology , 1998 .

[8]  P. Gray,et al.  A 1 . 5V , 10-bit , 14 . 3-MS / s CMOS Pipeline Analog-to-Digital Converter , 1999 .