FPGA Implementation of Genetic Algorithm for UAV Real-Time Path Planning

The main objective of an Unmanned-Aerial-Vehicle (UAV) is to provide an operator with services from its payload. Currently, to get these UAV services, one extra human operator is required to navigate the UAV. Many techniques have been investigated to increase UAV navigation autonomy at the Path Planning level. The most challenging aspect of this task is the re-planning requirement, which comes from the fact that UAVs are called upon to fly in unknown environments. One technique that out performs the others in path planning is the Genetic Algorithm (GA) method because of its capacity to explore the solution space while preserving the best solutions already found. However, because the GA tends to be slow due to its iterative process that involves many candidate solutions, the approach has not been actively pursued for real time systems. This paper presents the research that we have done to improve the GA computation time in order to obtain a path planning generator that can recompile a path in real-time, as unforeseen events are met by the UAV. The paper details how we achieved parallelism with a Field Programmable Gate Array (FPGA) implementation of the GA. Our FPGA implementation not only results in an excellent autonomous path planner, but it also provides the design foundations of a hardware chip that could be added to an UAV platform.

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