An FPGA-Accelerated Doppler Parameters Estimation Engine for Real-Time Synthetic Aperture Radar Imaging System

In this paper, we demonstrate an achievable implementation of Doppler parameters estimation engine. Taking advantage of FPGA, a highly parallelized and reconfigurable structure with a unified calculation is adopted. We build a prototype using single off-the-shelf Xilinx XC6VSX315T FPGA to verify the proposed method in a 16384 ×16384 SAR imaging process. The experiment result can achieve more than 20x time speedups over CPU-based solution, and the FPGA hardware resources can be balanced.