Elastic, elastic‐plastic and creep analyses of wafer level chip scale package solder joints on microvia build‐up printed circuit boards

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

[1]  Recent advances on a wafer-level flip chip packaging process , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[2]  Sa-Yoon Kang,et al.  Optimal structure of wafer level package for the electrical performance , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[3]  J. Lau,et al.  Creep behaviors of flip chip on board with 96.5Sn-3.5Ag and 100In lead-free solder joints , 2000 .

[4]  Herbert Reichl,et al.  Board level reliability of a waferlevel CSP using stacked solder spheres and a solder support structure (S/sup 3/) , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[5]  J. H. Lau Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability , 2002 .

[6]  John H. Lau,et al.  Nonlinear fracture mechanics analysis of wafer level chip scale package solder joints with cracks , 2000 .

[7]  John H. Lau,et al.  Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies , 2001 .

[8]  P. Garrou,et al.  Wafer level chip scale packaging (WL-CSP): an overview , 2000, ECTC 2000.

[9]  H. Reichl,et al.  Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[10]  J. H. Lau,et al.  Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis , 2000 .

[11]  John H. Lau,et al.  An overview of microvia technology , 2000 .

[12]  Yutaka Tsukada,et al.  Surface laminar circuit packaging , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.

[13]  J. Lau,et al.  Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board , 2000, Packaging of Electronic and Photonic Devices.

[14]  K. Banerji,et al.  Constitutive relations for tin-based-solder joints , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.

[15]  J. Lau Ball Grid Array Technology , 1994 .

[16]  John H. Lau,et al.  A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints , 2000, Packaging of Electronic and Photonic Devices.

[17]  A.R. Mirza One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[18]  John H. Lau,et al.  Chip on Board: Technologies for Multichip Modules , 1995 .

[19]  J. Lau,et al.  Thermal Stress and Strain in Microelectronics Packaging , 1993 .

[20]  D.C. O'Brien,et al.  Fabrication of wafer level chip scale packaging for optoelectronic devices , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).

[21]  N. Kelkar,et al.  A manufacturing perspective of wafer level CSP , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[22]  J. Lau,et al.  Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications , 2000, Packaging of Electronic and Photonic Devices.

[23]  Thomas Oppert,et al.  Wafer level CSP using low cost electroless redistribution layer , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[24]  J. Lau,et al.  Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies , 1996 .