Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses

The paper proposes a bus architecture which improves the performance and/or power dissipation of online buses. The proposed architecture reduces the delay on alternate lines by lowering its repeaters' threshold voltages, V/sub t/. Furthermore, the shifting of the signal switching on adjacent lines reduces the worst-case coupling capacitance. Two implementations of this bus architecture are proposed, the alternate-V/sub t/ (AVT) and the alternate forward body bias (ABB) schemes, and are compared to a conventional bus (CB) scheme. For a flop distance of 1800 /spl mu/m, the proposed schemes use the gained delay slack to reduce the total device width, thus reducing the energy dissipation by 31.2%. For a 500 ps cycle time, the proposed bus schemes increase the maximum distance between flip-flops by 33%.

[1]  T. Sakurai,et al.  Two schemes to reduce interconnect delay in bi-directional and uni-directional buses , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[2]  Taewhan Kim,et al.  Coupling delay optimization by temporal decorrelation using dual threshold voltage technique , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[3]  James Tschanz,et al.  Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors , 2002, DAC '02.

[4]  Anantha Chandrakasan,et al.  A bus energy model for deep submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Uming Ko,et al.  Hybrid dual-threshold design techniques for high-performance processors with low-power features , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[6]  Takayasu Sakurai,et al.  Coupling-driven bus design for low-power application-specific systems , 2001, DAC '01.

[7]  M. Khellah,et al.  Static pulsed bus for on-chip interconnects , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[8]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[9]  S. Narendra,et al.  Forward body bias for microprocessors in 130nm technology generation and beyond , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[10]  Hiroto Yasuura,et al.  A bus delay reduction technique considering crosstalk , 2000, DATE '00.