A 22nm dynamically adaptive clock distribution for voltage droop tolerance

A 22nm all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage (VCC) droops on microprocessor performance and energy efficiency. Silicon measurements demonstrate simultaneous throughput gains and energy reductions ranging from 14% and 3% at 1.0V to 31% and 15% at 0.6V, respectively, for a 10% VCC droop.