Novel Approach for Multiple Arbitrary Faults Diagnosis in Combinational Circuits

With the advent of VLSI, very complex circuits can be implemented in a single chip. So the need for testing the chip increases with the integration. Fault diagnosis results in improving the circuit design process, the manufacturing yield, cost of testing and also reduces the time to market. Diagnosis of today's complex faults is a challenging problem due to the explosion of the underlying solution space with the increasing number of fault locations.This paper gives a comprehensive framework for logic diagnosis of multiple arbitrary faults that can occur in combinational digital circuits. This approach employs the effect cause analysis for the fault diagnosis .To demonstrate the applicability of the proposed method stuck at faults ,bridging faults, open-interconnect fault, stuck open faults, delay faults and a combination of these faults in the same circuit simultaneously leading to multiple faults are dealt with

[1]  Arnaud Virazel,et al.  A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects , 2010, IEEE Transactions on Computers.

[2]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[3]  Raimund Ubar,et al.  Parallel fault backtracing for calculation of fault coverage , 2008, 2008 Asia and South Pacific Design Automation Conference.

[4]  Ernst G. Ulrich,et al.  Concurrent simulation of nearly identical digital networks , 1974, Computer.

[5]  R. D. Blanton,et al.  Universal fault simulation using fault tuples , 2000, Proceedings 37th Design Automation Conference.

[6]  John P. Hayes,et al.  On the properties of the input pattern fault model , 2003, TODE.

[7]  Tracy Larrabee,et al.  Diagnosing realistic bridging faults with single stuck-at information , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Douglas B. Armstrong,et al.  A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.

[9]  Jürgen Alt,et al.  Deterministic test generation for non-classical faults on the gate level , 1995, Proceedings of the Fourth Asian Test Symposium.

[10]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[11]  Xiaoqing Wen,et al.  VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon) , 2006 .

[12]  Hans-Joachim Wunderlich,et al.  Adaptive Debug and Diagnosis without Fault Dictionaries , 2007, ETS.

[13]  D. M. H. Walker,et al.  A fast algorithm for critical path tracing in VLSI digital circuits , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[14]  I. Pomeranz,et al.  On testing of interconnect open defects in combinational logic circuits with stems of large fanout , 2002, Proceedings. International Test Conference.

[15]  Xinyue Fan,et al.  A novel stuck-at based method for transistor stuck-open fault diagnosis , 2005, IEEE International Conference on Test, 2005..

[16]  Wu-Tung Cheng,et al.  Differential Fault Simulation - A Fast Method Using Minimal Memory , 1989, 26th ACM/IEEE Design Automation Conference.

[17]  Irith Pomeranz On pass/fail dictionaries for scan circuits , 2001, Proceedings 10th Asian Test Symposium.

[18]  Srikanth Venkataraman,et al.  Poirot: Applications of a Logic Fault Diagnosis Tool , 2001, IEEE Des. Test Comput..

[19]  Andreas G. Veneris,et al.  Design diagnosis using Boolean satisfiability , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[20]  Premachandran R. Menon,et al.  Critical Path Tracing - An Alternative to Fault Simulation , 1983, 20th Design Automation Conference Proceedings.

[21]  Andreas G. Veneris,et al.  Incremental fault diagnosis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Kazuki Shigeta,et al.  An improved fault diagnosis algorithm based on path tracing with dynamic circuit extraction , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[23]  Raimund Ubar,et al.  Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs , 2007, 12th IEEE European Test Symposium (ETS'07).

[24]  Bernd Becker,et al.  Simulating Resistive-Bridging and Stuck-At Faults , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  P. Goel Test Generation Costs Analysis and Projections , 1980, 17th Design Automation Conference.