High frequency performance of dual metal gate vertical tunnel field effect transistor based on work function engineering

A novel dual metal gate doping-less vertical tunnel field effect transistor (D-VTFET) on silicon body, using work function engineering is proposed. The proposed structure does not required impurity doping for formation of the drain and the source regions. In this concern, source and drain regions are formed by selecting appropriate work-function of metal electrode. The source and drain regions are not formed by conventional ways of ion implantation or diffusion. Hence, proposed structure is immune greatly to the process variation, issues of doping control and random dopant fluctuations which are serious problems in ultrathin silicon devices. For further improvement in ON state current and analogue/RF figures of merit dual work function of single gate material is considered. The electrical characteristics of the proposed device with the D-VTFET are simulated and compared.

[1]  M. J. Kumar,et al.  Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device , 2012, IEEE Transactions on Electron Devices.

[2]  Dopingless super-steep impact ionisation MOS (dopingless-IMOS) based on workfunction engineering , 2014 .

[3]  K. K. Bourdelle,et al.  $\Omega$-Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs , 2012, IEEE Electron Device Letters.

[4]  M. H. Vasantha,et al.  Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping , 2016, IEEE Transactions on Electron Devices.

[5]  M. J. Kumar,et al.  Doping-Less Tunnel Field Effect Transistor: Design and Investigation , 2013, IEEE Transactions on Electron Devices.

[6]  Zhijiong J. Luo,et al.  Performance Improvement of ${\rm HfO}_{2}/{\rm SrTiO}_{3}$ Hetero-Oxide Transistors Using Argon Bombardment , 2013, IEEE Electron Device Letters.

[7]  Wei Wang,et al.  Germanium–Tin P-Channel Tunneling Field-Effect Transistor: Device Design and Technology Demonstration , 2013, IEEE Transactions on Electron Devices.

[8]  Y. Hao,et al.  Design of GeSn-Based Heterojunction-Enhanced N-Channel Tunneling FET With Improved Subthreshold Swing and ON-State Current , 2015, IEEE Transactions on Electron Devices.

[9]  Mamidala Jagadesh Kumar,et al.  In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor , 2014, IEEE Electron Device Letters.

[10]  Subhasis Haldar,et al.  Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation , 2014, Microelectron. J..

[11]  M. Jagadesh Kumar,et al.  Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer , 2015, Scientific Reports.

[12]  Ji Shi,et al.  The interaction between platinum films and silicon substrates: Effects of substrate bias during sputtering deposition , 2000 .

[13]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.