Hardware implementation of a Viterbi decoder using the minimal trellis

McEliece and Lin introduced the minimal trellis for convolutional codes, which can be considerably less complex than the conventional trellis typically used to construct Viterbi decoders. The authors state that this reduced trellis complexity can lead to less complex Viterbi decoders in practice. In this paper, we compare conventional and minimal Viterbi decoders for a rate 2/3 convolutional code considered by McEliece and Lin, which possesses a minimal trellis with half of the complexity of the conventional trellis. The decoder circuits were implemented in Altera programmable logic devices. We show that, though the complexity measure used by McEliece and Lin does not translate directly to practice, reductions in power consumption and hardware utilization, along with increased maximum operating frequency, can indeed be obtained for the decoders.

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