An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS

This brief presents an 8-bit 350-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with 1.5 b/cycle redundancy in 65-nm CMOS. With 12.5% redundancy in conversion cycles, conversion errors caused by capacitor mismatch, offset and DAC settling errors can be addressed. Compared to the conventional 1.5 b/cycle operation, the proposed switching removes the pre-set phase and thus reduces the speed and power penalty. Besides, with this switching scheme, only two reference voltages are needed instead of five in the conventional scheme. The prototype achieves 45.7 dB SNDR at Nyquist input and consumes 2.1 mW from a 1.2 V supply, resulting in a Walden FoM of 38.1 fJ/conversion-step.

[1]  Nan Sun,et al.  A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration , 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

[2]  Rui Paulo Martins,et al.  A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration , 2018, IEEE Journal of Solid-State Circuits.

[3]  Yintang Yang,et al.  A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Hsin-Shu Chen,et al.  A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Jeyanandh Paramesh,et al.  Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  N. P. van der Meijs,et al.  A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios , 2011, IEEE Journal of Solid-State Circuits.

[7]  Tsung-Han Tsai,et al.  An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Chirn Chye Boon,et al.  A 4.06 mW 10-bit 150 MS/s SAR ADC With 1.5-bit/cycle Operation for Medical Imaging Applications , 2018, IEEE Sensors Journal.

[9]  Ho-Jin Park,et al.  A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC , 2015, IEEE Journal of Solid-State Circuits.

[10]  Franco Maloberti,et al.  An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC , 2012, IEEE Journal of Solid-State Circuits.