Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications

This paper focuses on the application of low temperature bonding to the fabrication of three-dimensional (3D) massively parallel signal processors for high performance infrared imagers. We review two generations of the 3D heterogeneous integration process. The first generation process, compatible with pixel sizes in the 20 to 30 µm range, relies on low temperature epoxy bonding that is followed by the formation of copper-filled through-silicon vias (TSVs). The second generation process, scalable to pixel sizes of 10 µm and smaller, employs solid–liquid diffusion bonding of copper–tin to copper at 250 °C; the bonding follows TSV fabrication. To demonstrate the second generation process, we fabricated 3D test vehicles in the form of 640 × 512 arrays of vertical interconnects composed of TSVs and metal–metal bonds on a 10 µm pitch. We characterized electrical conductivity of the interconnects, the isolation resistance between the interconnects, and the operability and yield of the arrays. The successful demonstration of the interconnect technology paves the way to a functional demonstration of 3D signal processors in infrared imagers with 10 µm pixels.

[1]  K. Suganuma,et al.  Joining of alumina short-fibre reinforced AA6061 alloy to AA6061 alloy and to itself , 1987 .

[2]  M. B. Naik,et al.  CVD of copper using copper(I) and copper(II) β-diketonates , 1995 .

[3]  P. Ramm,et al.  Vertical System Integration by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding , 2004 .

[4]  Stuart Horn,et al.  Progress in the development of vertically integrated sensor arrays (Invited Paper) , 2005, SPIE Defense + Commercial Sensing.

[5]  C. Bower,et al.  High Density 3-D Integration Technology for Massively Parallel Signal Processing in Advanced Infrared Focal Plane Array Sensors , 2006, 2006 International Electron Devices Meeting.

[6]  D. Malta,et al.  Bonding for 3-D Integration of Heterogeneous Technologies and Materials , 2008, ECS Transactions.

[7]  R. Gutmann,et al.  Wafer Level 3-D ICs Process Technology , 2008 .

[8]  Karen Willcox,et al.  Kinetics and kinematics for translational motions in microgravity during parabolic flight. , 2009, Aviation, space, and environmental medicine.

[9]  A. Jourdain,et al.  Cu to Cu interconnect using 3D-TSV and wafer to wafer thermocompression bonding , 2010, 2010 IEEE International Interconnect Technology Conference.

[10]  D. Malta,et al.  Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[11]  R. Labie,et al.  Fine pitch Cu/Sn solid state diffusion bonding for making high yield bump interconnections and its application in 3D integration , 2010, 3rd Electronics System Integration Technology Conference ESTC.

[12]  Scott Jordan,et al.  Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications , 2010, Security + Defence.

[13]  H. Noma,et al.  IMC bonding for 3D interconnection , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[14]  D. Temple,et al.  Reliability and ultra-low temperature bonding of high density large area arrays with Cu/Sn-Cu interconnects for 3D integration , 2010, 2010 IEEE International Interconnect Technology Conference.

[15]  A. Jourdain,et al.  Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[16]  E. Beyne,et al.  Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[17]  Walied A. Moussa,et al.  A packaging solution utilizing adhesive-filled TSVs and flip–chip methods , 2012 .

[18]  D. Temple,et al.  High Density Metal–Metal Interconnect Bonding for 3-D Integration , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[19]  S. Ramaswami,et al.  Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[20]  Joel Silberman,et al.  A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias , 2012, 2012 IEEE International Solid-State Circuits Conference.

[21]  P. Chausse,et al.  Electrical and morphological assessment of via middle and backside process technology for 3D integration , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[22]  D. Temple,et al.  High-Density Large-Area-Array Interconnects Formed by Low-Temperature Cu/Sn–Cu Bonding for Three-Dimensional Integrated Circuits , 2012, IEEE Transactions on Electron Devices.

[23]  C. Laviron,et al.  WSS and ZoneBOND temporary bonding techniques comparison for 80μm and 55μm functional interposer creation , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[24]  M. Barkey,et al.  Analyzing the behavior and shear strength of common adhesives used in temporary wafer bonding , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[25]  A. Jourdain,et al.  Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[26]  J. Robinson,et al.  Case for small pixels: system perspective and FPA challenge , 2014, Sensing Technologies + Applications.

[27]  R. Alapati,et al.  Challenges to via middle TSV integration at sub-28nm nodes , 2014, IEEE International Interconnect Technology Conference.

[28]  Christopher M. Masterjohn,et al.  Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics , 2014, Sensing Technologies + Applications.