An efficient circuit-level power reduction technique for ultralow power applications

This research work explores various circuit-level design techniques to identify the best technique suitable for low power circuit design. To establish a proper performance comparison, reported techniques are implemented in a transmission gate-based carry skip adder circuit @ 22-nm technology node. Results obtained demonstrate that the multi-threshold CMOS technique offers the best performance under the given conditions. Further, a novel modified hybrid circuit design technique is also proposed in this paper. To validate the proposed design technique, performance metrics of the carry-skip adder circuit implemented using the proposed hybrid technique and other low power circuit design techniques are compared. Obtained results establish that the proposed technique offers improvement in terms of propagation delay (TP), average power dissipation (PAVG), power delay product (PDP) and leakage power (LP), when compared with its counterpart at a supply voltage of 0.4 V.

[1]  T. Sakurai,et al.  A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current , 2000, IEEE Journal of Solid-State Circuits.

[2]  Manoj Kumar,et al.  A New Low Power Single Bit Full Adder Design with 14 Transistors using Novel 3 Transistors XOR Gate , 2012 .

[3]  Aminul Islam,et al.  Performance Enhancement of Full Adder Circuit: Current Mode Operated Majority Function Based Design , 2018 .

[4]  Yong-Bin Kim,et al.  CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits , 2011, IEEE Transactions on Nanotechnology.

[5]  Kaushik Roy.  Leakage power reduction in low-voltage CMOS designs , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[6]  S. A. Abbasi,et al.  Optimized Design of a 32-nm CNFET-Based Low-Power Ultrawideband CCII , 2012, IEEE Transactions on Nanotechnology.

[7]  Ken Choi,et al.  Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design , 2011, IEEE Transactions on Nanotechnology.

[8]  A. Afzali-Kusha,et al.  Study of super cut-off CMOS technique in presence of the gate leakage current , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

[9]  Punam Bedi,et al.  Load Balancing on Dynamic Network Using Mobile Process Groups , 2007, 15th International Conference on Advanced Computing and Communications (ADCOM 2007).

[10]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[11]  R. Anjana,et al.  Analysis of sub threshold leakage reduction techniques in deep sub micron regime for CMOS VLSI circuits , 2013, 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT).

[12]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[13]  H. Wong,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.

[14]  Massimo Alioto,et al.  Analysis and comparison on full adder block in submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[15]  K. David Solomon Raj,et al.  Sleepy Keeper Approach for Power Performance Tuning in VLSI Design , 2013 .

[16]  Suman Mamidi,et al.  A low-power carry skip adder with fast saturation , 2004 .

[17]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[18]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[19]  P. K. Dakhole,et al.  VLSI design of power efficient Carry Skip Adder using TSG & Fredkin reversible gate , 2012, 2012 International Conference on Devices, Circuits and Systems (ICDCS).

[20]  Aminul Islam,et al.  Nonvolatile and Robust Design of Content Addressable Memory Cell Using Magnetic Tunnel Junction at Nanoscale Regime , 2015, IEEE Transactions on Magnetics.

[21]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[22]  Mehdi Kamal,et al.  High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  R. Paily,et al.  Leakage Reduction by Modified Stacking and Optimum ISO Input Loading in CMOS Devices , 2007, 15th International Conference on Advanced Computing and Communications (ADCOM 2007).

[24]  N. Ranganathan,et al.  LECTOR: a technique for leakage reduction in CMOS circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Kaamran Raahemifar,et al.  A 14-transistor low power high-speed full adder cell , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[26]  Aminul Islam,et al.  Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application , 2015 .

[27]  Jie Deng,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking , 2007, IEEE Transactions on Electron Devices.

[28]  Aminul Islam,et al.  Robust Design of CNFET Based Buffered Delay Model and Microwave Pulse Generator , 2014, 2014 International Conference on Devices, Circuits and Communications (ICDCCom).