An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and $-$98 dB THD

A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. Realized in a 0.18 mum CMOS technology, it provides 81 dB SNDR, 82 dB dynamic range, and -98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 V power supply (analog power 4.4 mW, digital power 3.7 mW). Its figure-of-merit is 0.25 pJ/conversion-step, which is among the best reported for discrete-time delta-sigma ADCs in wideband applications.

[1]  I. Galton,et al.  An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[2]  Gabor C. Temes,et al.  Noise-Coupled Multi-Cell Delta-Sigma ADCs , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[3]  I. Mehr,et al.  A 500 msample/s 6–bit Nyquist rate ADC for disk drive read channel applications , 1998 .

[4]  Thomas Burger,et al.  A 0.13/spl mu/m CMOS EDGE/UMTS/WLAN Tri-Mode /spl Delta//spl Sigma/ ADC with -92dB THD , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  Andreas Kaiser,et al.  Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping , 2001, IEEE J. Solid State Circuits.

[6]  Gabor C. Temes,et al.  Enhanced split-architecture delta-sigma ADC , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[7]  Michael M. Miyamoto,et al.  A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique , 2006, IEEE Custom Integrated Circuits Conference 2006.

[8]  Gabor C. Temes,et al.  A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR , 2008, IEEE Journal of Solid-State Circuits.

[9]  Gabor C. Temes,et al.  An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD , 2009, IEEE J. Solid State Circuits.

[10]  Mohamed Dessouky,et al.  Very low-voltage digital-audio /spl Delta//spl Sigma/ modulator with 88-dB dynamic range using local switch bootstrapping , 2001 .

[11]  Gabor C. Temes,et al.  Noise-Coupled Delta-Sigma ADCS , 2011 .

[12]  Kenneth W. Martin,et al.  High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[13]  Miyamoto Masayuki,et al.  A 80/100 MS/s 76.3/70.1-dB SNDR ΔΣ ADC for digital TV receivers , 2006 .

[14]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[15]  Franco Maloberti,et al.  A 5.4mW 2-Channel Time-Interleaved Multi-bit /spl Delta//spl Sigma/ Modulator with 80dB SNR and 85dB DR for ADSL , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[16]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[17]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[18]  I. Mehr,et al.  A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 1999, IEEE Journal of Solid-State Circuits.

[19]  Franco Maloberti,et al.  3.4 A 14mW Multi-bit ∆Σ Modulator with 82dB SNR and 86dB DR for ADSL2+ , 2006 .