Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process

Abstract A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide effectively in nanoscaled integrated circuits. This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers. The failure current can be improved by 23.5% compared with traditional GGNMOS.

[1]  Yan Han,et al.  Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application , 2010 .

[2]  Yan Han,et al.  Design analysis of novel substrate-triggered GGNMOS in 65nm CMOS process , 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

[3]  R. Gauthier,et al.  Process and design optimization of a protection scheme based on NMOSFETs with ESD implant in 65nm and 45nm CMOS technologies , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[4]  G. Groeseneken,et al.  A compact model for the grounded-gate nMOS behaviour under CDM ESD stress , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[5]  B. Keppens,et al.  Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[6]  Mu-Chun Wang,et al.  ESD protection for the tolerant I/O circuits using PESD implantation , 2002 .

[7]  Michiel Steyaert,et al.  Dynamic substrate resistance snapback triggering of ESD protection devices , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[8]  Lining Zhang,et al.  Investigation of LOCOS- and Polysilicon-Bound Diodes for Robust Electrostatic Discharge (ESD) Applications , 2010, IEEE Transactions on Electron Devices.

[9]  Tung-Yang Chen,et al.  Substrate-triggered technique for on-chip ESD protection design in a 0.18-/spl mu/m salicided CMOS process , 2003 .

[10]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[11]  Charvaka Duvvury,et al.  Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes , 1995, Proceedings of International Electron Devices Meeting.

[12]  E. Rosenbaum,et al.  A dual-base triggered SCR with very low leakage current and adjustable trigger voltage , 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.