New Validation and Test Problems for High Performance Deep Sub-micron VLSI Circuits

This tutorial will focus on (1) the new validation and test issues, (2) basic models and analysis of the related underlying electrical phenomena, (3) techniques to generate tests for validation and testing, which would take into account these issues, and (4) several real-life case studies. The primary factors causing a paradigm shift in the area of validation and test that will be discussed are (1) deep submicron CMOS technology, (2) high performance system architecture, (3) short rise/fall times of signals, and (4) variations in electrical parameter values due to process variations. These factors influence R, L, C, dI/dt, and dV/dt values, which in turn impact ground bounce and clock skew and cause crosstalk and overshoots and undershoots. In turn, these impact performance.