A FPGA-based hardware implementation of generalized profile search using online arithmetic

This paper describes the hardware implementation of the Generalized Profile Search algorithm using online arithmetic and redundant, data representation. This is part of the GenStorm project, aimed at providing a dedicated computer for biological sequence processing based on reconfigurable hardware using FPGAs. The serial evaluation of the result made possible by a redundant data representa.tion leads to a significant increase of data throughput in comparison with standard non redundant data coding.

[1]  Gianluca Tempesti,et al.  Embryonics: The Birth of Synthetic Life , 1995, Towards Evolvable Hardware.

[2]  C. Piguet,et al.  Life Organization as a Source of Inspiration for Self-Repairing VLSI , 1997 .

[3]  Amos Bairoch,et al.  The PROSITE dictionary of sites and patterns in proteins, its current status , 1993, Nucleic Acids Res..

[4]  Eduardo Sanchez,et al.  Beyond superscalar using FPGAs , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[5]  Moshe Sipper,et al.  From configurable circuits to bio-inspired systems , 2000 .

[6]  Axel Jantsch,et al.  Hardware/Software Cosynthesis for Reconfigurable Systems , 1996 .

[7]  C. Piguet,et al.  Genomic Cellular Automata Transposed on Silicon: Experiments in Synthetic Life , 1996 .

[8]  Christof Teuscher,et al.  A Revival of Turing's Forgotten Connectionist Ideas: Exploring Unorganized Machines , 2000, NCPW.

[9]  Eduardo Sanchez,et al.  BIOWATCH: une montre autoréparable et autoreproductrice , 1996 .

[10]  R.K. Singh,et al.  BioSCAN: a VLSI-based system for biosequence analysis , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[11]  Peter F. Corbett,et al.  Digit-serial processing techniques , 1990 .

[12]  J.-O. Haenni,et al.  Une plate-forme pour l"enseignement et le prototypage d"architectures reconfigurables , 1999 .

[13]  Moshe Sipper,et al.  Static and Dynamic Configurable Systems , 1999, IEEE Trans. Computers.

[14]  Marco Tomassini,et al.  Phylogeny, Ontogeny, and Epigenesis: Three Sources of Biological Inspiration for Softening Hardware , 1996, ICES.

[15]  Eduardo Sanchez,et al.  An On-Line Arithmetic-Based Reconfigurable Neuroprocessor , 1999, IPPS/SPDP Workshops.

[16]  E. Sanchez,et al.  Development and prototyping system far an 8-bit multitask micropower processor , 1995, Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype.

[17]  C. Piguet,et al.  An 8-bit multitask micropower RISC core , 1994 .

[18]  E. Sanchez,et al.  Implementation of neural constructivism with programmable hardware , 1996, 1st International Symposium on Neuro-Fuzzy Systems, AT '96. Conference Report.

[19]  Jean-Michel Muller,et al.  Some Operators for On-Line Radix-2 Computations , 1994, J. Parallel Distributed Comput..

[20]  Stefan Monnier,et al.  Etude d'implémentation d'un processeur du type SMT (Simultaneous Multithreaded) , 1999 .

[21]  C. Iseli,et al.  SPYDER: un processeur reconfigurable réalisé à l'aide de circuits FPGA , 1997 .

[22]  Eduardo Sanchez,et al.  A C++ compiler for FPGA custom execution units synthesis , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[23]  Arnaud Tisserand,et al.  FPGA implementation of real-time digital controllers using on-line arithmetic , 1997, FPL.

[24]  Christian Piguet,et al.  Embryonics: Designing Programmable Circuits with Biological-like Properties , 1994, Applied Informatics.

[25]  Jean-Cédric Chappelier,et al.  An FPGA-based coprocessor for the parsing of context-free grammars , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[26]  Jean-Cédric Chappelier,et al.  Towards NLP-coprocessing: An FPGA implementation of a context-free parser , 2000 .

[27]  A. Perez,et al.  The FAST architecture: a neural network with flexible adaptable-size topology , 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

[28]  Christof Teuscher,et al.  Self-Organizing Topology Evolution of Turing Neural Networks , 2001, ICANN.

[29]  Gianluca Tempesti,et al.  Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[30]  E. Sanchez,et al.  Speeding-up adaptive heuristic critic learning with FPGA-based unsupervised clustering , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[31]  Christof Teuscher,et al.  A tool for teaching and research on computer architecture and reconfigurable systems , 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

[32]  E. Mosanya,et al.  Arithmétique en ligne pour l'implémentation matérielle de la recherche de motifs par Profils Généralisés , 1999 .

[33]  J. Lindy Books , 1985, The Lancet.

[34]  E. Sanchez,et al.  Neural Network Structure Optimization through On-line Hardware Evolution , 1996 .

[35]  Eduardo Sanchez,et al.  Spyder: a reconfigurable VLIW processor using FPGAs , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[36]  Amos Bairoch,et al.  The PROSITE database, its status in 1997 , 1997, Nucleic Acids Res..

[37]  Christian Miccio Parallel Genetic Programming Induction of Binary Decision Diagrams , .

[38]  M S Waterman,et al.  Identification of common molecular subsequences. , 1981, Journal of molecular biology.

[39]  Moshe Sipper,et al.  Quo Vadis evolvable hardware? , 1999, CACM.

[40]  Andrés Pérez-Uribe,et al.  Structure-Adaptable Neurocontrollers: A Hardware-Friendly Approach , 1997, IWANN.

[41]  Dominique Lavenier,et al.  Systolic filter for fast DNA similarity search , 1995, Proceedings The International Conference on Application Specific Array Processors.

[42]  Eduardo Sanchez,et al.  A platform for co-design and co-synthesis based on FPGA , 1996, Proceedings Seventh IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype.

[43]  E. Sanchez,et al.  Blackjack as a test bed for learning strategies in neural networks , 1998, 1998 IEEE International Joint Conference on Neural Networks Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98CH36227).

[44]  Dzung T. Hoang,et al.  Searching genetic databases on Splash 2 , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[45]  Kevin Karplus,et al.  A Flexible Motif Search Technique Based on Generalized Profiles , 1996, Comput. Chem..

[46]  Andrés Pérez-Uribe,et al.  FPGA Implementation of a Network of Neuronlike Adaptive Elements , 1997, ICANN.

[47]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[48]  Marco Tomassini,et al.  The firefly machine: online evolware , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[49]  Eduardo Sanchez,et al.  Hardware implementation of generalized profile search on the GENSTORM machine , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[50]  A. D. McLachlan,et al.  Profile analysis: detection of distantly related proteins. , 1987, Proceedings of the National Academy of Sciences of the United States of America.

[51]  Christof Teuscher,et al.  Romero"s Odyssey to Santa Fe: from Simulation to Real Life , 2000 .

[52]  Amos Bairoch,et al.  A Generalized Profile Syntax for Biomolecular Sequence Motifs and its Function in Automatic Sequence Interpretation , 1994, ISMB.

[53]  Gianluca Tempesti,et al.  Guest Editors' Introduction: Von Neumann's Legacy: Special Issue on Self-Replication , 1998, Artificial Life.

[54]  Christof Teuscher,et al.  A networked FPGA-based hardware implementation of a neural network application , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[55]  Eduardo Sanchez,et al.  An in-system routing strategy for evolvable hardware programmable platforms , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[56]  Bertrand Mesot,et al.  Solving Partially Observable Problems by Evolution and Learning of Finite State Machines , 2001, ICES.

[57]  Joan Cabestany,et al.  A configurable hardware platform for implementing bio-inspired hardware models , 2001 .

[58]  Daniel P. Lopresti Rapid implementation of a genetic sequence comparator using field-programmable logic arrays , 1991 .

[59]  F. J. Gomez,et al.  Teaching Digital Systems Using Dynamic Reconfiguration , 1999 .

[60]  Christof Teuscher,et al.  A reconfigurable platform for academic purposes , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[61]  Christof Teuscher,et al.  CryptoBooster: A Reconfigurable and Modular Cryptographic Coprocessor , 1999, CHES.

[62]  Kevin Karplus USING MARKOV MODELS AND HIDDEN MARKOV MODELS TO FIND REPETITIVE EXTRAGENIC PALINDROMIC SEQUENCES IN ESCHERICHIA COLI , 1994 .

[63]  Eduardo Sanchez,et al.  A Comparison of Reinforcement Learning with Eligibility Traces and Integrated Learning, Planning and Reacting , 1999 .

[64]  Abraham Kandel,et al.  Intelligent systems and interfaces , 2000 .

[65]  Marco Tomassini,et al.  Online Autonomous Evolware , 1996, ICES.

[66]  D. P. Lopresti Discounts for dynamic programming with applications in VLSI processor arrays , 1987 .

[67]  Daniel P. Lopresti,et al.  P-NAC: A Systolic Array for Comparing Nucleic Acid Sequences , 1987, Computer.

[68]  Eduardo Sanchez,et al.  RENCO: a reconfigurable network computer , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[69]  J.-O. Haenni,et al.  RENCO: un ordinateur de réseau reconfigurable , 1997 .

[70]  Moshe Sipper,et al.  Configurable Chips Meld Software and Hardware , 2000, Computer.

[71]  Eduardo Sanchez,et al.  A Study of a Simultaneous Multithreaded Processor Implementation , 1999, Euro-Par.

[72]  Andrés Pérez-Uribe,et al.  FPGA Implementation of an Adaptable-Size Neural Network , 1996, ICANN.

[73]  Kishor S. Trivedi,et al.  On-line algorithms for division and multiplication , 1975, 1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH).

[74]  Marco Tomassini,et al.  The POE Model of Bio-Inspired Hardware Systems: A Short Introduction , 1997 .

[75]  Benoît Garbinato,et al.  An Algotronix FPGAs Development System on Mac , 1993 .

[76]  Eduardo Sanchez,et al.  CAFCA (Compact Accelerator For Cellular Automata): the metamorphosable machine , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[77]  Kevin Karplus,et al.  A ?ex-ible search technique based on generalized profiles , 1996 .

[78]  Andrés Pérez-Uribe,et al.  Structure Adaption in Artificial Neural Networks through Adaptive Clustering and through Growth in State Space , 1999, IWANN.

[79]  Yves Robert,et al.  Algorithmes et architectures systoliques , 1989 .

[80]  Josep Llosa,et al.  Low-Power VLIW Processors: A High-Level Evaluation , 1998 .

[81]  Gianluca Tempesti,et al.  A new paradigm for developing digital systems based on a multi-cellular organization , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[82]  Christof Teuscher,et al.  Une comparaison entre quelques implantations logicielles et matérielles de l"algorithme de chiffrement IDEA , 2000 .

[83]  Eduardo Sanchez,et al.  Leonardo and Discipulus Simplex: An Autonomous, Evolvable Six-Legged Walking Robot , 1999, IPPS/SPDP Workshops.

[84]  Marco Tomassini,et al.  A phylogenetic, ontogenetic, and epigenetic view of bio-inspired hardware systems , 1997, IEEE Trans. Evol. Comput..

[85]  Marco Tomassini,et al.  Towards Evolvable Hardware: The Evolutionary Engineering Approach , 1996 .