Design Procedure and Selection of TIQ Comparators for Flash ADCs

In this work, we propose a novel procedure to generate and select threshold inverter quantized (TIQ) comparators for TIQ Flash ADCs. The new procedure generates more TIQ comparators than the procedure designed by Lee , Yoo, and Choi (LYC) (Proceedings of International Symposium on Quality Electronic Design, 2002). Two 6-bit TIQ Flash ADCs were designed, the LYC flash ADC, which selects its TIQ comparators using the current threshold selection algorithm, and the AC TIQ Flash ADC, which selects its TIQ comparators using the threshold selection algorithm proposed herein. Both ADCs were designed in $$0.5\,{\upmu }\hbox {m}$$0.5μm CMOS technology and compared against the process, voltage source, and temperature (PVT) variations. Proposed TIQ selection procedure allows the designer to select the optimum TIQ set for desired ADC. AC ADC has a DNL values ±0.015 LSB and INL values between $$\pm 0.0225$$±0.0225 compared to ±0.1 LSB and 0.3 to −0.1 LSB for DNL and INL values of the LYC ADC. ENOB and SNDR for the AC were improved by at least $$31.3\%$$31.3% compared to LYC ADC, at typical process settings. For process, voltage source, and temperature (PVT) variations, in overall the AC ADC has at least better the DNL values by at least $$22.5\%$$22.5% and reduced INL values by at least $$35\%$$35%. Over PVT variation, AC ADC has maintained ENOB value greater than 5.3 bits for all 16 variation corners. ENOB was improved by at least 1.5 bits over all corners. SNDR and SFDR were increased by at least 4 dB over the PVT corners. Proposed AC procedure shows scalability feature by generating extra threshold points for the $$65\hbox {-nm}$$65-nm TIQ comparators.

[1]  A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[2]  Kurt Keutzer,et al.  Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Kyusun Choi,et al.  “The CMOS Inverter” as a Comparator in ADC Designs , 2004 .

[4]  Kyusun Choi,et al.  A power and resolution adaptive flash analog-to-digital converter , 2002, ISLPED '02.

[5]  Wasim Arif,et al.  A power efficient 6-bit TIQ ADC design for portable applications , 2013, 2013 IEEE Third International Conference on Consumer Electronics ¿ Berlin (ICCE-Berlin).

[6]  Kumar Y. B. Nithin,et al.  Design of Low Power 5-Bit Hybrid Flash ADC , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[7]  Abhishek Kumar,et al.  Design of low power 0.8V Flash ADC using TIQ in 90nm technology , 2015, 2015 International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM).

[8]  Manish Kumar,et al.  Design of an efficient 8-bit flash ADC for optical communication receivers , 2016, 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT).

[9]  Sandeep Saini,et al.  A 4-bit, 3.2 GSPS flash analog to digital converter with a new multiplexer based encoder , 2014, 2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).

[10]  Zhangming Zhu,et al.  A Low Offset High Speed Comparator for Pipeline ADC , 2013, J. Circuits Syst. Comput..

[11]  Kyusun Choi,et al.  Design method and automation of comparator generation for flash A/D converter , 2002, Proceedings International Symposium on Quality Electronic Design.

[12]  Zhangming Zhu,et al.  A Low Offset Comparator for High Speed Low Power ADC , 2013, J. Circuits Syst. Comput..

[13]  M. S. Bhat,et al.  Design of Resolution Adaptive TIQ Flash ADC using AMS 0.35μm technology , 2008, 2008 International Conference on Electronic Design.

[14]  A. Abumurad,et al.  Increasing the ADC precision with oversampling in a flash ADC , 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

[15]  Lei Zhao,et al.  A High Speed Low Power latched Comparator for SHA-Less Pipelined ADC , 2013, J. Circuits Syst. Comput..

[16]  Behzad Razavi.  CMOS technology characterization for analog and RF design , 1999 .

[17]  Prasanna Palsodkar,et al.  Improved power supply rejection (PSR) digital comparator based Flash analog to digital converter (FADC) , 2014, 2014 International Conference on Electronics and Communication Systems (ICECS).

[18]  Iyappan Perumal,et al.  Design of Analog to Digital Converter Using CMOS Logic , 2009, 2009 International Conference on Advances in Recent Technologies in Communication and Computing.

[19]  Hongchin Lin,et al.  A Low-Voltage Process Corner Insensitive Subthreshold CMOS Voltage Reference Circuit , 2006, 2006 IEEE International Conference on IC Design and Technology.

[20]  Jaume Segura,et al.  A variable threshold voltage inverter for CMOS programmable logic circuits , 1998 .

[21]  Burhan Khurshid,et al.  A 7GS/s, 1.2 V. pseudo logic encoder based flash ADC using TIQ technique , 2015, 2015 Annual IEEE India Conference (INDICON).

[22]  C. C. McAndrew,et al.  Understanding MOSFET mismatch for analog design , 2003 .

[23]  Reetika K. Agarwal,et al.  A low-power Flash quantizer using Inverter threshold reference and dual mode operation , 2014, 2014 International Conference on Electronics and Communication Systems (ICECS).

[24]  Mamun Bin Ibne Reaz,et al.  An Improved A Low Power CMOS TIQ Comparator Flash ADC , 2014 .

[25]  Kyusun Choi,et al.  Fat tree encoder design for ultra-high speed flash A/D converters , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[26]  Neeta Tripathi,et al.  Adiabatic Threshold Inverter Quantizer for a 3-bit Flash ADC , 2016, 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET).

[27]  Roohie Naaz Mir,et al.  A 4 GS/s, 1.8 V multiplexer encoder based flash ADC using TIQ technique , 2014, 2014 International Conference on Signal Processing and Integrated Networks (SPIN).

[28]  Kyusun Choi,et al.  A tiq-based cmos flash a/d converter for system-on-chip applications , 2003 .

[29]  Liang-Teck Pang,et al.  Impact of Layout on 90nm CMOS Process Parameter Fluctuations , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..