Models and methods of inter-gate resynthesis at the transistor level for nanoelectronic circuits based on FinFETs

Sharing the methods of logical and physical synthesis can be an effective solution of the nanoelectronic circuits design problem. The logical resynthesis has a significant effect on the subsequent design efficiency. To solve this problem, models and methods of inter-gate resynthesis at the transistor level were developed earlier at the IPPM RAS. Proposed methods was adopted for structural optimization based on information about physical implementation of FinFET circuits. An effective algorithm of structural optimization was developed. A new layout description model based on the SP graph extension was proposed. In this case, degrees of freedom is retained due to the boolean graph, and high accuracy of power and area calculation is achieved through structural interpretation at the transistor level. According to preliminary estimates, the reduction in the area with the proposed approach will be about 20–30% compared to the results of the synthesis in commercial CAD systems.