An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP), Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of ≫ 150 μm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. A folded-patch antenna with dimensions of 2.5x2.5x1 mm3, operating at 5.7 GHz was analysed considering a 10 kΩ-cm HRPS wafer. The antenna has a -10 dB return loss bandwidth of 50 MHz and an efficiency of 58 %, a performance comparable to glass substrates.

[1]  A. Chandrakasan,et al.  Power aware wireless microsensor systems , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[2]  Jan Rabaey,et al.  Ultra low-energy transceivers for wireless sensor networks , 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

[3]  P.M. Mendes,et al.  Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[4]  P.M. Mendes,et al.  An integrated folded-patch antenna for wireless microsystems , 2004, Proceedings of IEEE Sensors, 2004..

[5]  James H. Aylor,et al.  Computer for the 21st Century , 1999, Computer.

[6]  Pasqualina M. Sarro,et al.  Substrate options and add-on process modules for monolithic RF silicon technology , 2002, Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting.

[7]  J. Burghartz,et al.  Processability and electrical characteristics of glass substrates for RF wafer-level chip-scale packages , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..