Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

In this paper we present novel recharged logic for multiple-valued (MV) systems by utilizing semi-floating-gate (SFG) transistors. The recharged multiple-valued logic can be used to implement low-power digital circuits. The improvement in power dissipation is mainly in reduced dynamic power dissipation. The main purpose is to level out the power dissipated by a digital system to obtain more suitable logic for mixed mode design.

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