Dimensioning of an ATM Switch with Shared Buffer and Threshold Priority

A number of recent studies have addressed the use of priority mechanisms in Asynchronous Transfer Mode (ATM) switches. This investigation concerns the performance evaluation and dimensioning of a shared-buffer switching element with a threshold priority mechanism (partial buffer sharing). It assumes that incoming ATM ceils are distinguished by a space priority assignment, i.e., loss of a high priority cell should be less likely than loss of a low priority cell. The evaluation method is analytic, based on an approximate discrete-time, finite-state Markov model of a switch and its incoming traffic. The development focuses on the formulation of steady-state loss probabilities for each priority class. Evaluation of delay measures for each class is also supported by the model; results concerning the latter are illustrated without development. The analysis of loss probabilities is then used to dimension the buffer capacity and threshold level such that required maximum cell loss probabilities are just satisfied for each cell type. Moreover, when so dimensioned with respect to relatively stringent loss requirements, i.e., probabilities of 10 10 and 10 s for high and low priority cells, respectively, we find that both loss performance and resource utilization are appreciably improved over a comparable switch without such a mechanism.