The early assessment of the fault tolerance mechanisms is an essential task in the design of dependable computing systems. Simulation languages offer the necessary support to carry out such a task. Due to its wide spectrum of application and hierarchical features, VHDL is a powerful simulation language. This chapter summarizes the main results of a pioneering effort aimed at developing and experimenting supporting tools for fault injection into VHDL models. The chapter first identifies the possible means to inject faults into a VHDL model. Then, we describe two prototype tools that were developed using each of the main injection strategies previously identified. Finally, some general insights and perspectives are briefly discussed.