A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops

This paper presents a charge pump-phase locked loop (CP-PLL) that utilizes a frequency-modulated analog-to-digital converter (FM-ADC) as part of a calibration circuit to compensate for process variations and intemperate operating environments. The calibration circuitry first detects the shift in operating conditions, and then dynamically adjusts the loop bandwidth back to its nominal range to guarantee phase lock for all four process corners and the typical case, and across the telecommunications temperature range of 0 to 80 degC. Calibration comes at the expense of a worst case increase in lock time of 15% and increase of close-in phase noise of 13% for the PLL architecture examined. This self-calibrating PLL, including the FM-ADC, are designed and laid out in TSMC's 0.18-mum RF CMOS process (TSMC18RF).

[1]  William F. Egan,et al.  Frequency synthesis by phase lock , 1981 .

[2]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[3]  Andrew Richardson,et al.  Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers , 2004 .

[4]  Jin-Sheng Wang,et al.  A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[5]  M. Ismail,et al.  CMOS PLL calibration techniques , 2004, IEEE Circuits and Devices Magazine.

[6]  C. G. Sodini,et al.  A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated /spl Sigma/-/spl Delta/ frequency synthesizer , 2002 .

[7]  Ook Kim,et al.  A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching , 2001, IEEE J. Solid State Circuits.

[8]  Martin Margala,et al.  6-bit low power low area frequency modulation based flash ADC , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[9]  Mohammed Ismail,et al.  A 4 Ghz 0.18um CMOS PLL Frequency Synthesizer withWide-Band VCO for Multi-Standard Wireless Applications , 2003 .

[10]  Xie Juan A Low Power Fully Programmable 1 MHz Resolution 2 . 4 GHz CMOS PLL Frequency Synthesizer , 2022 .

[11]  Brian Ellis Low‐voltage CMOS RF Frequency Synthesizers , 2005 .

[12]  Gerald E. Sobelman,et al.  Comparison of LC and Ring VCOs for PLLs in a 90 nm Digital CMOS Process , 2006 .

[13]  Un-Ku Moon,et al.  A CMOS self-calibrating frequency synthesizer , 2000, IEEE Journal of Solid-State Circuits.

[14]  Mani Soma,et al.  An all-digital built-in self-test for high-speed phase-locked loops , 2001 .

[15]  Beomsup Kim,et al.  A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

[16]  Martin Margala,et al.  Process tolerant calibration circuit for PLL applications with BIST , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[17]  Aubin Roy,et al.  An automated, complete, structural test solution for SERDES , 2004, 2004 International Conferce on Test.

[18]  Sungho Kang,et al.  An efficient all-digital built-in self-test for chargepump PLL , 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.