Worst-case execution time analysis for modern hardware architectures

Knowing the worst case execution times (WCETs) for programs are crucial for the design and veri cation of real-time systems. Modern hardware architectures utilize pipelined execution and cache memory for improved performance. We extend an existing execution time analysis technique, the Implicit Path Enumeration Technique (IPET), to consider these and other modern hardware architecture features. We extend IPET in two stages. First, we annotate the control ow graph of the program with variables representing the history of execution, thus allowing the state of architectural entities, such as cache and pipeline, to be determined before each basic block. Secondly, we model the architectural entities with constraints. The result is an equation which contains a complete model of how the program will execute on the modeled architecture. This novel idea provides a straightforward and exible way of incorporating the behavior of various modern hardware architecture features into WCET analysis.