The paper describes GRAPE-II (Graphical RApid Prototyping Environment), an advanced system level development environment for the specification, compilation, debugging, simulation and emulation of complete DSP applications. GRAPE-II fully supports the real-time emulation of synchronous multi-rate applications on heterogeneous target platforms, consisting of multiple TMS320C40 processors, DSP5600x processors, core processors and Xilinx FPGAs. Ports to the TMS320C80 and the Analog Devices 21060 are foreseen for the near future. GRAPEII also allows for the simulation and debugging of asynchronous as well as synchronous multi-rate applications on a single Unix workstation, on a Unix workstation cluster, on a Meiko Computing Surface and on a Parsytec Xplorer parallel machine. GRAPE-II is commercialised under the name Virtuoso Synchro by Intelligent Systems International. Development costs for such ASICs are high, so algorithms should be thoroughly tested and optimized before implementation at all design stages. To verify and optimize algorithms, algorithms have to be specified first and their functionality has to be tested completely. Then, the optimum signal widths are determined, balancing cost with noise and disturbances. Finally, this optimized algorithm is transformed into an architecture for implementation. During the last step, the compatibility of the implementation with the original algorithm is verified. Nowadays, most tests and optimizations are performed by analysis and simulation tools on workstations or super-minicomputers. Application prototypes are worked out only during the last design stage. However, if we prototype in the earlier stages of the design, we can • test more parameters in a shorter time • optimize variables under real-time conditions Index Terms — Rapid prototyping, digital signal processing, parallel processing, data flow, programming environments. • evaluate an algorithm's subjective qualities, e.g. by listening to the actual results of the algorithm; this puts a real-time constraint onto the prototyping
[1]
Rudy Lauwereins,et al.
Geometric parallelism and cyclo-static data flow in GRAPE-II
,
1994,
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping.
[2]
Jean A. Peperstraete,et al.
PDG: a process-level debugger for concurrent programs in the GRAPE rapid prototyping environment
,
1993,
[1993] Proceedings The Fourth International Workshop on Rapid System Prototyping.
[3]
Rudy Lauwereins,et al.
Buffer memory requirements in DSP applications
,
1994,
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping.
[4]
Rudy Lauwereins,et al.
Design of a processing board for a programmable multi-VSP system
,
1993,
J. VLSI Signal Process..
[5]
Rudy Lauwereins,et al.
GRAPE-II: a tool for the rapid prototyping of multi-rate asynchronous DSP applications on heterogeneous multiprocessors
,
1992,
[1992 Proceedings] The Third International Workshop on Rapid System Prototyping.
[6]
Rudy Lauwereins,et al.
Compile time analysis to minimise runtime overhead in pre-emptive scheduling on multi-processors
,
1994
.
[7]
M. Engels,et al.
Development of a load balancing tool for the GRAPE rapid prototyping environment
,
1993,
[1993] Proceedings The Fourth International Workshop on Rapid System Prototyping.
[8]
Rudy Lauwereins,et al.
Paradigm RP, a System for the Rapid Prototyping of Real-Time DSP Applications
,
1994
.
[9]
Edward A. Lee,et al.
Software synthesis for DSP using ptolemy
,
1995,
J. VLSI Signal Process..
[10]
M. Alard,et al.
Principles of Modulation and Channel Coding for Digital Broadcasting for Mobile Receivers
,
1987
.