Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography

In this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix- 2 interleaved algorithm is proposed to reduce the time complexity of conventional interleaved modular multiplication. The proposed multiplication algorithm is designed in hardware and separately implemented on Xilinx Virtex-7, Virtex-6, Virtex-5, and Virtex-4 field-programmable gate array (FPGA) platforms. On the Virtex-7 FPGA, the proposed design occupies only 1151, 1409, 1491, 2355, and 2496 look up tables (LUTs) and performs single modular multiplication in 0.93 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, 1.18 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, 1.45 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, 2.80 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, and 4.69 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> with maximum clock frequencies of 207.1 MHz, 190.7 MHz, 177.3 MHz, 137.6 MHz, and 111.2 MHz over five NIST prime fields of size 192, 224, 256, 384, and 521 bits, respectively. The hardware implementations on the Virtex-6, Virtex-5, and Virtex-4 FPGAs also show that the proposed design is highly efficient in terms of hardware resource utilization and area-delay product compared with other designs for modular multiplication.