SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits
暂无分享,去创建一个
[1] Bernard N. Sheehan. ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization , 1999, DAC '99.
[2] Jian Wang,et al. SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[3] Ngai Wong,et al. Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[4] Lawrence T. Pileggi,et al. Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Lawrence T. Pileggi,et al. SPIE: sparse partial inductance extraction , 1997, DAC.
[6] Roland W. Freund,et al. SPRIM: structure-preserving reduced-order interconnect macromodeling , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[7] Sheldon X.-D. Tan,et al. Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form , 2007, 2007 Asia and South Pacific Design Automation Conference.
[8] Tatjana Stykel,et al. Gramian-Based Model Reduction for Descriptor Systems , 2004, Math. Control. Signals Syst..
[9] B. Moore. Principal component analysis in linear systems: Controllability, observability, and model reduction , 1981 .
[10] Hao Ji,et al. How to efficiently capture on-chip inductance effects: introducing a new circuit element K , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[11] Luís Miguel Silveira,et al. Guaranteed passive balancing transformations for model order reduction , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Sheldon X.-D. Tan,et al. Wideband passive multiport model order reduction and realization of RLCM circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Roland W. Freund,et al. Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.
[14] Luís Miguel Silveira,et al. Exploiting input information in a model reduction algorithm for massively coupled parasitic networks , 2004, Proceedings. 41st Design Automation Conference, 2004..
[15] Alan J. Laub,et al. Controllability and Observability Criteria for Multivariable Linear Second-Order Models , 1983, 1983 American Control Conference.
[16] Hao Ji,et al. KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect , 2001, ASP-DAC '01.
[17] Sheldon X.-D. Tan,et al. Advanced Model Order Reduction Techniques in VLSI Design , 2007 .
[18] D. G. Meyer,et al. Balancing and model reduction for second-order form linear systems , 1996, IEEE Trans. Autom. Control..
[19] Lawrence T. Pileggi,et al. PRIMA: passive reduced-order interconnect macromodeling algorithm , 1998, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[20] Sheldon X.-D. Tan. A general hierarchical circuit modeling and simulation algorithm , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[21] J. Phillips,et al. Poor man's TBR: a simple model reduction scheme , 2005 .
[22] Cheng-Kok Koh,et al. Passivity-preserving model reduction via a computationally efficient project-and-balance scheme , 2004, Proceedings. 41st Design Automation Conference, 2004..