Address decoder faults and their tests for two-port memories

A two-port memory contains two duplicated sets of address decoders which operate independently. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling are investigated. Fault models and their tests are introduced, together with the test strategy.

[1]  Michel Renovell,et al.  The concept of resistance interval: a new parametric model for realistic resistive bridging fault , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[2]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[3]  Michael Nicolaidis,et al.  Testing complex couplings in multiport memories , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Said Hamdioui,et al.  Fault models and tests for two-port memories , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[5]  Benoit Nadeau-Dostie,et al.  Serial interfacing for embedded-memory testing , 1990, IEEE Design & Test of Computers.

[6]  Manuel J. Raposa.  Dual port static RAM testing , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.