A design of a compact 2 GHz-PLL with a new adaptive active loop filter circuit

This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 /spl mu/m-CMOS process. The total chip area of the PLL is reduced to 1/2 of previous one. The jitter performance is almost equal to conventionally biased PLL.

[1]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[2]  John G. Maneatis.  PLL Based on Self-Biased Techniques , 1996 .

[3]  M. Sumita,et al.  A 400MHz 32b embedded microprocessor core AM34-1 with 4.0GB/s cross-bar bus switch for SoC , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[4]  M. Steyaert,et al.  A fully integrated CMOS DCS-1800 frequency synthesizer , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[5]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[6]  강수진.  Charge-Pump Phase-Locked Loops에 관한 연구 및 회로 설계 , 1996 .

[7]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz lock range for microprocessors , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz of lock range for microprocessors , 1992 .