Irregular-Mapped Protograph LDPC-Coded Modulation: A Bandwidth-Efficient Solution for 5G Networks with Massive Data-Storage Requirement

The huge amount of data produced in the fifthgeneration (5G) networks not only brings new challenges to the reliability and efficiency of mobile devices but also drives rapid development of new storage techniques. With the benefits of fast access speed and high reliability, NAND flash memory has become a promising storage solution for the 5G networks. In this paper, we investigate a protograph-coded bit-interleaved coded modulation with iterative detection and decoding (BICM-ID) utilizing irregular mapping (IM) in the multi-level-cell (MLC) NAND flashmemory systems. First, we propose an enhanced protograph-based extrinsic information transfer (EPEXIT) algorithm to facilitate the analysis of protograph codes in the IM-BICM-ID systems. With the use of EPEXIT algorithm, a simple design method is conceived for the construction of a family of high-rate protograph codes, called irregular-mapped accumulate-repeat-accumulate (IMARA) codes, which possess both excellent decoding thresholds and linearminimum-distance-growth property. Furthermore, motivated by the voltage-region iterative gain characteristics of IM-BICM-ID systems, a novel read-voltage optimization scheme is developed to acquire accurate read-voltage levels, thus minimizing the decoding thresholds of protograph codes. Theoretical analyses and errorrate simulations indicate that the proposed IMARA-aided IMBICM-ID scheme and the proposed read-voltage optimization scheme remarkably improve the convergence and decoding performance of flash-memory systems. Thus, the proposed protographcoded IM-BICM-ID flash-memory systems can be viewed as a reliable and efficient storage solution for the new-generation mobile networks with massive data-storage requirement.

[1]  Wei Shao,et al.  Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  H. Vincent Poor,et al.  Secrecy Performance Analysis of Distributed Asynchronous Cyclic Delay Diversity-Based Cooperative Single Carrier Systems , 2020, IEEE Transactions on Communications.

[3]  Gerhard Bauch,et al.  Bit-interleaved coded irregular modulation , 2006, Eur. Trans. Telecommun..

[4]  Shu Lin,et al.  A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Liang Shi,et al.  Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory , 2019, IEEE Transactions on Computers.

[6]  Karine Amis,et al.  Optimized Rate-Adaptive Protograph-Based LDPC Codes for Source Coding With Side Information , 2018, IEEE Transactions on Communications.

[7]  Yong Liang Guan,et al.  Read and Write Voltage Signal Optimization for Multi-Level-Cell (MLC) NAND Flash Memory , 2016, IEEE Transactions on Communications.

[8]  Pingping Chen,et al.  Rate-Adaptive Protograph LDPC Codes for Multi-Level-Cell NAND Flash Memory , 2018, IEEE Communications Letters.

[9]  Yong Liang Guan,et al.  Design Guidelines of Low-Density Parity-Check Codes for Magnetic Recording Systems , 2018, IEEE Communications Surveys & Tutorials.

[10]  Miaowen Wen,et al.  A Survey on Spatial Modulation in Emerging Wireless Systems: Research Progresses and Applications , 2019, IEEE Journal on Selected Areas in Communications.

[11]  Yong Liang Guan,et al.  Decision-Directed Retention-Failure Recovery With Channel Update for MLC NAND Flash Memory , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Lin Wang,et al.  Performance of improved AR3A code over EPR4 channel , 2011, 2011 3rd International Conference on Computer Research and Development.

[13]  Leszek Szczecinski,et al.  Modulation doping for iterative demapping of bit-interleaved coded modulation , 2005, IEEE Communications Letters.

[14]  Tong Zhang,et al.  Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Aria Nosratinia,et al.  The design of rate-compatible protograph LDPC codes , 2010, 2010 48th Annual Allerton Conference on Communication, Control, and Computing (Allerton).

[16]  Chaitali Chakrabarti,et al.  Product Code Schemes for Error Correction in MLC NAND Flash Memories , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Stephan ten Brink,et al.  Design of low-density parity-check codes for modulation and detection , 2004, IEEE Transactions on Communications.

[18]  Can Zhang,et al.  Irregular mapping design for bit-interleaved coded modulation with low complexity iterative decoding , 2016, 2016 6th International Conference on Electronics Information and Emergency Communication (ICEIEC).

[19]  Sandra Sendra,et al.  A Survey on 5G Usage Scenarios and Traffic Models , 2020, IEEE Communications Surveys & Tutorials.

[20]  Huang-Chang Lee,et al.  LDPC coded modulation for TLC flash memory , 2017, 2017 IEEE Information Theory Workshop (ITW).

[21]  Zhaocheng Wang,et al.  Irregular Mapping and its Application in Bit-Interleaved LDPC Coded Modulation With Iterative Demapping and Decoding , 2011, IEEE Transactions on Broadcasting.

[22]  Aleksandar Kavcic,et al.  Optimal Detector for Multilevel NAND Flash Memory Channels with Intercell Interference , 2014, IEEE Journal on Selected Areas in Communications.

[23]  Guoan Bi,et al.  A Survey on Protograph LDPC Codes and Their Applications , 2015, IEEE Communications Surveys & Tutorials.

[24]  Lingjun Kong,et al.  Page-Based Dynamic Partitioning Scheduling for LDPC Decoding in MLC NAND Flash Memory , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

[25]  Marco Chiani,et al.  Protograph LDPC Codes Design Based on EXIT Analysis , 2007, IEEE GLOBECOM 2007 - IEEE Global Telecommunications Conference.

[26]  Lara Dolecek,et al.  A Combinatorial Methodology for Optimizing Non-Binary Graph-Based Codes: Theoretical Analysis and Applications in Data Storage , 2017, IEEE Transactions on Information Theory.

[27]  Marco Gramaglia,et al.  A Machine Learning Approach to 5G Infrastructure Market Optimization , 2020, IEEE Transactions on Mobile Computing.

[28]  Harald Haas,et al.  Index Modulation Techniques for Next-Generation Wireless Networks , 2017, IEEE Access.

[29]  Navrati Saxena,et al.  Next Generation 5G Wireless Networks: A Comprehensive Survey , 2016, IEEE Communications Surveys & Tutorials.

[30]  Miaowen Wen,et al.  Generalized Multiple-Mode OFDM With Index Modulation , 2018, IEEE Transactions on Wireless Communications.

[31]  Seokin Hong,et al.  Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[32]  Tong Zhang,et al.  On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  Richard D. Wesel,et al.  Enhanced Precision Through Multiple Reads for LDPC Decoding in Flash Memories , 2013, IEEE Journal on Selected Areas in Communications.

[34]  Giuseppe Caire,et al.  Bit-Interleaved Coded Modulation , 2008, Found. Trends Commun. Inf. Theory.

[35]  Mohsen Guizani,et al.  Design of Protograph-LDPC-Based BICM-ID for Multi-Level-Cell (MLC) NAND Flash Memory , 2019, IEEE Communications Letters.