A study of phase noise and jitter in submicron CMOS phase-locked loop circuits

[1]  H. Ichino,et al.  Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX , 2002 .

[2]  Eiji Takeda,et al.  Hot-Carrier Effects in MOS Devices , 1995 .

[3]  V. Kroupa,et al.  Noise Properties of PLL Systems , 1982, IEEE Trans. Commun..

[4]  G. Gerosa,et al.  A wide-bandwidth low-voltage PLL for PowerPC microprocessors , 1995 .

[5]  Ashok Srivastava,et al.  Phase noise analysis for OFDM systems based on hot-carrier effects in synchronization electronics , 2005, SPIE International Symposium on Fluctuations and Noise.

[6]  Chih-Kong Ken Yang,et al.  Methodology for on-chip adaptive jitter minimization in phase-locked loops , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[7]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[8]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[9]  Chi Zhang,et al.  OFDM performance analysis in the presence of synchronization errors induced by hot carriers , 2005, VTC-2005-Fall. 2005 IEEE 62nd Vehicular Technology Conference, 2005..

[10]  V. von Kaenel,et al.  A 4-GHz clock system for a high-performance system-on-a-chip design , 2001 .

[11]  Chenming Hu,et al.  Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.

[12]  C.-H. Lee,et al.  Wide-band CMOS VCO and frequency divider design for quadrature signal generation , 2004, 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535).

[13]  Resve Saleh,et al.  Analysis and design of digital integrated circuits : in deep submicron technology , 2003 .

[14]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[15]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[16]  A. Hajimiri,et al.  Noise in phase-locked loops , 2001, 2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475).

[17]  P. Nilsson,et al.  A digitally controlled PLL for SoC applications , 2004, IEEE Journal of Solid-State Circuits.

[18]  D. Boerstler A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz , 1999, IEEE J. Solid State Circuits.

[19]  D. Leeson A simple model of feedback oscillator noise spectrum , 1966 .

[20]  J. Stensby,et al.  Phase-Locked Loops: Theory and Applications , 1997 .

[21]  Ashok Srivastava,et al.  Phase noise analysis for ICI self-cancellation coded OFDM with short-channel synchronization devices , 2005, GLOBECOM '05. IEEE Global Telecommunications Conference, 2005..

[22]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[23]  Ashok Srivastava,et al.  HOT CARRIER EFFECTS ON JITTER PERFORMANCE IN CMOS VOLTAGE-CONTROLLED OSCILLATORS , 2006 .

[24]  E. Xiao,et al.  Hot carrier and soft breakdown effects on VCO performance , 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

[25]  M. J. Deen,et al.  Effects of hot-carrier stress on the performance of the LC-tank CMOS oscillators , 2003 .

[26]  S.A. Saller,et al.  Reliability effects on MOS transistors due to hot-carrier injection , 1985, IEEE Transactions on Electron Devices.

[27]  Hsiao-Chun Wu,et al.  Hot-electron-induced effects on noise and jitter in submicron CMOS phase-locked loop circuits , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[28]  Chih-Kong Ken Yang,et al.  Jitter optimization based on phase-locked loop design parameters , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[29]  S. Pellerano,et al.  A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider , 2004, IEEE Journal of Solid-State Circuits.

[30]  G. Gerosa,et al.  A Wide-Bandwidth Low-Voltage Pll for Powerpc Microprocessors , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[31]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[32]  Chetan Shambhulinga Salimath Design of CMOS LC voltage controlled oscillators , 2006 .

[33]  Ashok Srivastava,et al.  Hot carrier effects on jitter and phase noise in CMOS voltage-controlled oscillators , 2005, SPIE International Symposium on Fluctuations and Noise.

[34]  Kyoohyun Lim,et al.  A low-noise phase-locked loop design by loop bandwidth optimization , 2000, IEEE Journal of Solid-State Circuits.

[35]  K.A. Jenkins,et al.  A 26.5 GHz silicon MOSFET 2:1 dynamic frequency divider , 2000, IEEE Microwave and Guided Wave Letters.

[36]  Douglas L. Maskell,et al.  Adaptive subsample delay estimation using a modified quadrature phase detector , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[37]  A.M. Fahim Jitter analysis of digital frequency dividers in communication systems , 2004, Proceedings of the 2004 IEEE International Frequency Control Symposium and Exposition, 2004..

[38]  Paul V. Brennan Phase-Locked Loops: Principles and Practice , 1996 .

[39]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[40]  Yuan Chen,et al.  Hot-carrier-induced circuit degradation for 0.18 /spl mu/m CMOS technology , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[41]  Dan H. Wolaver,et al.  Phase-Locked Loop Circuit Design , 1991 .

[42]  Ashok Srivastava,et al.  Hot Carrier Effects in Wireless Communication Systems Built on Short-Channel MOSFETs , 2007, IEEE Transactions on Wireless Communications.

[43]  Young-Shig Choi,et al.  An adaptive bandwidth phase locked loop with locking status indicator , 2005, Proceedings. The 9th Russian-Korean International Symposium on Science and Technology, 2005. KORUS 2005..

[44]  Amit Mehrotra,et al.  Noise analysis of phase-locked loops , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[45]  John McNeill,et al.  Jitter in ring oscillators , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[46]  Yiyan Wu,et al.  OFDM performance analysis in the phase noise arising from the hot-carrier effect , 2006, IEEE Transactions on Consumer Electronics.

[47]  V. Boccuzzi,et al.  A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver , 2005, IEEE Journal of Solid-State Circuits.

[48]  H. Ichino,et al.  PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits , 2004, IEEE Journal of Solid-State Circuits.

[49]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation, Second Edition , 2004 .

[50]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[51]  Chenming Hu,et al.  Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.

[52]  S. Minehane,et al.  Evolution of BSIM3v3 parameters during hot-carrier stress , 1997, 1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319).