Digital detection with asynchronous sampling using amplitude error prediction

This work concerns low complexity methods which allow sampling detectors to operate asynchronously at a rate only slightly higher than the synchronous sampling rate. There are several motivating factors for using a fixed rate sampling clock compared to conventional phase locked loop methods which use a variable rate sampling clock. We explain a few of these factors along with describing two different approaches for performing timing recovery with asynchronous samples. The first approach, which is usually used, is an interpolation based approach. The second approach is based on predicting amplitude error that is due to sampling phase error. Simulation results are presented along with discussion comparing the different methods.