Incremental physical design

" # $ &% ')( +*, ! /. 0 # 21 3/ 4 657* 0 1 89 3 :;: / ?A@9 BC. DE FG H # cH #! 3N !> AB_ HW H A ! # U\ Ve :[!" 3/ T Ve%9')( 3JV"3J 3 f:a # 3c -" / A ! $ # d?g h H #3 ! !> B, : 9 G? 1. INTRODUCTION K!" 3/ j \ &4 e%9')( [ H ! 3 FG4 / 3&4 3/ A # U F UkR: / nm o p qr?Tb ) 3/3/3&3/UH 3cB_ .7 4 3J s 6 -" I tVum v w xNy"wUq7F9 3/3J k^ ! # 4j 3/ 2m zEo x_v {"x,y | qrF` / 3/ 3/3/ .7 ZI> H D Lm o p"x p y qrF`!> B, N 3/! gm w o x;} } q7F= # I # tVQ eV" # 6m ~ wUq7F f H A 6 c # :X 3Z € 3/ 4 4W \ 4 U 65a%9')( /89* 0 1 3 ? 0 H T3 T F+ # U.7 . A kE C!" 3/3/9 #3 #D 4R H [ / 3/ 4 i A 3J / 4 3J 3; 3/ # " C " 3/ 4 A H " 4 3 m {"x+w w x o o x ~ ~ x p |"x p"w qr? ‚G V F* 0 1ƒ 3AH DE LI> €3/ f c A 3/3 . " !> V„ 9 H R3JV"3J Y.7 DE aF>H #4 H .7 DE aF+ 4 .7 # DE aFd # V /.7 DE [m } y qrF= HWB_ HQ 3N B_ Q3/ N :_3JV" H 3/ 3 FODE U . GF… „ V"3/ 39 .73/ ? †= H„ ]BC N :` H RI 4 ! j P H i H 3/ ‡ k 4e H ˆ 4 H U ?‰*, Y. ! \" Vf :9! 3/ Y f U\" T4 6% '…(" 3JV"3J ˆ Y. ! # 6B_ Hg DE K 3/ 4 g! 3/3/ 3„ 3Z:a 6 g A V ! \2!" Št 3N l 3 DE /V2 ‹ R = 3/ 4 4 H 3 j H 4 3 ?Y ] #4 H 3 N T3J ? ‚;H U C #3= 3/ / T U C T H C 9 :> " "V" A i3J / -" 3T Q #4 H 3 ?j W H \ N3/ . GF>B; R # c AI Œ Vc3/DE UVc H B_ Hj4 & ! H 3/ #3 c H Y :O! H V 3/ ) " 3/ 4 d?`ŽW 9B_ H c:X T D # 3… U V"3/ 3] 3J A R : H = 3/3 ?) 3J. 3/39 kE NI k .7 / Uk 4YB_ H 9H D 4Y # # L5X: # A 4 G4E 3/ !> / O &3/H C3/ m v p qr? t #4 H 3_:X 93JV" H 3/ #3[ c # V -" 9 " B_H „ 3/ 4 i4 3_ #  # d H 4 3 ?;‘[: H 3/ G UH 4 3C A " [ R , T G H 4 A H 3/ #4 dF / U , / 3= O A kE ` # !" DE 3) N 9 :O H R 3/ #4 2l tVc / 3 ?9’c UH #3/ 3[ &  / H ,!> / 3] : H , 3/ 4 R H O ; U\ !> 3/ :X 9 ! $ Qm y qr? 0 L ‹Y 9 4 H 39 R " Z I" R4 T U E3/ 3] # N [3/H / O : # ? ’i V& DE ; #4 H 3…3/HN 3)3/ T # 4 F :X U Q 4 H 3 F` e A $ 4„ QI> A 3/ VQ ". P QH „ _Œ ! # 4 F!  F -" 4 ?“‚;H W A # ” H 4 Q 3i 6 " # eB_H UH‰!> / :R H e 3/ 4 ” H cB, e 6 € ! ! V€ H 3/ K 4 H 3c hB_H c 3A H jl V • 3/!> P / S]? 0 3/ A 9 NI> :9 3/ H€ 3/3Z € H „ e :& _ # V -" AH DE I> !> / R V F :X 3/ 4 RŒ !  # 4Ym o } q7F ! # . im w ~ qrF_ hb]M`– 0 4Pm o { x9p } qr?6 ; 4 !" #$ iH 3CI> c3J " L em y x>v v qrF B_H # m ~ q… " 3/3/ 3 —,1 1ƒ !" #$ f3/ 4e P `3/ :  # # VT! . € 3  UH 4 3Z c A Z K H i 3/ #4 d? 0 B; k€ ˜m o | q&! 3/ 3L g  UH 4 V6 A ! ! # 4 4 H ƒ:X 9'd™9‚,.7I 3/ „b]M,– 0 H  A 3_ H R ! H . !" A tVP : H „ 3/ #4 d? 0 P C # 4W V"3/ 3 4 H ƒ 3!" 3/ c Wm ~ { qr?_b) # V F N 4 .7I 3/ c ". ]3/ UH # 4c " W 4 H “H 3&I> 2! U. 3/ Z # em z } qr? t L H & U\" C DE 3/I 3/ 3 F B, : !> 3J. 3/ I C3/ -" # 3 F R3J 4 !> Y!" I 3] N H 9 :> ". d! / # 4 F Œ !  # 4 F>! # F L -" /.

[1]  Prithviraj Banerjee,et al.  Optimization by simulated evolution with applications to standard cell placement , 1991, DAC '90.

[2]  Donald E. Thomas,et al.  Exploiting the special structure of conflict and compatibility graphs in high-level synthesis , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Robert K. Brayton,et al.  Planning for performance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[4]  Robert K. Brayton,et al.  Incremental methods for FSM traversal , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[5]  David Eppstein,et al.  Dynamic half-space reporting, geometric optimization, and minimum spanning trees , 1992, Proceedings., 33rd Annual Symposium on Foundations of Computer Science.

[6]  Chak-Kuen Wong,et al.  Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles , 1987, IEEE Transactions on Computers.

[7]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[8]  G. Ramalingam Bounded Incremental Computation , 1996, Lecture Notes in Computer Science.

[9]  Georg Sigl,et al.  GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Daniel Brand,et al.  BooleDozer: Logic synthesis for ASICs , 1996, IBM J. Res. Dev..

[11]  Majid Sarrafzadeh,et al.  Nostradamus: a floorplanner of uncertain designs , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[13]  C. L. Liu,et al.  A timing-constrained incremental routing algorithm for symmetrical FPGAs , 1996, Proceedings ED&TC European Design and Test Conference.

[14]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[15]  Jason Cong,et al.  Depth optimal incremental mapping for field programmable gate arrays , 2000, DAC.

[16]  Naveed A. Sherwani Algorithms for VLSI Physcial Design Automation , 1998 .

[17]  T. Ohtsuki,et al.  Recent advances in VLSI layout , 1990, Proc. IEEE.

[18]  Mostafa Abd-El-Barr,et al.  On the optimization of MOS circuits , 1993 .

[19]  Michael T. Goodrich,et al.  Dynamic trees and dynamic point location , 1991, STOC '91.

[20]  Jason Cong,et al.  An implicit connection graph maze routing algorithm for ECO routing , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[21]  Charles J. Alpert,et al.  The ISPD98 circuit benchmark suite , 1998, ISPD '98.

[22]  Thomas Lengauer,et al.  Integer Program formulations of Global Routing and Placement Problems , 1993, Algorithmic Aspects of VLSI Layout.

[23]  Naveed A. Sherwani,et al.  Algorithms for VLSI Physical Design Automation , 1999, Springer US.

[24]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[25]  Alessandro De Gloria,et al.  A Tile-Expansion Router , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Jason Cong,et al.  A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design , 1993, 30th ACM/IEEE Design Automation Conference.

[27]  Robert K. Brayton,et al.  Minimal logic re-synthesis for engineering change , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[28]  Seth Hutchinson,et al.  Efficient search and hierarchical motion planning by dynamically maintaining single-source shortest paths trees , 1995, IEEE Trans. Robotics Autom..

[29]  S. Sitharama Iyengar,et al.  Finding obstacle-avoiding shortest paths using implicit connection graphs , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Ralph H. J. M. Otten,et al.  Global wires: harmful? , 1998, ISPD '98.

[31]  C. Y. Lee An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[32]  G. Karypis,et al.  Multilevel k-way hypergraph partitioning , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[33]  Dana S. Richards,et al.  Distributed genetic algorithms for the floorplan design problem , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  D. T. Lee,et al.  On crossing minimization problem , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  Narendra V. Shenoy,et al.  The future of logic synthesis and physical design in deep-submicron process geometries , 1997, ISPD '97.

[36]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[37]  Frank O. Hadlock,et al.  A shortest path algorithm for grid graphs , 1977, Networks.

[38]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[39]  Hyunchul Shin,et al.  A simple yet effective technique for partitioning , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[40]  Majid Sarrafzadeh,et al.  An incremental floorplanner , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[41]  Dileep A. Divekar Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools , 1984 .

[42]  Keith A. Jenkins,et al.  Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor , 1998, IEEE J. Solid State Circuits.

[43]  Jason Cong,et al.  Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[44]  Jean-Yves Fourniols,et al.  Characterization of Crosstalk Noise in Submicron CMOS Integrated Circuits , 1998 .

[45]  Horst D. Simon,et al.  Fast multilevel implementation of recursive spectral bisection for partitioning unstructured problems , 1994, Concurr. Pract. Exp..

[46]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.

[47]  Yu-Chin Hsu,et al.  SILK: a simulated evolution router , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[48]  Raul Camposano The quarter micron challenge: intergrating physical and logic design , 1997, ISPD '97.

[49]  Asmus Hetzel,et al.  A sequential detailed router for huge grid graphs , 1998, Proceedings Design, Automation and Test in Europe.

[50]  Andrew B. Kahng,et al.  A general framework for vertex orderings with applications to circuit clustering , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[51]  Maurizio Rebaudengo,et al.  GALLO: a genetic algorithm for floorplan area optimization , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[52]  Majid Sarrafzadeh,et al.  Multi-center congestion estimation and minimization during placement , 2000, ISPD '00.

[53]  J. Cong,et al.  Multiway partitioning with pairwise movement , 1998, ICCAD '98.

[54]  John M. Emmert,et al.  Incremental routing in FPGAs , 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

[55]  Andrew B. Kahng,et al.  Improved algorithms for hypergraph bipartitioning , 2000, ASP-DAC '00.

[56]  Toshiyuki Shibuya,et al.  Touch and cross router , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[57]  Soha Hassoun,et al.  Fine grain incremental rescheduling via architectural retiming , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).

[58]  Frank M. Johannes,et al.  Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[59]  S. Grout,et al.  Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century , 1997, ISPD '97.

[60]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.

[61]  Malgorzata Marek-Sadowska,et al.  Crosstalk reduction for VLSI , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[62]  Andrew B. Kahng,et al.  A general framework for vertex orderings, with applications to netlist clustering , 1994, ICCAD '94.

[63]  Eby G. Friedman,et al.  Interconnect coupling noise in CMOS VLSI circuits , 1999, ISPD '99.

[64]  Majid Sarrafzadeh,et al.  An Introduction To VLSI Physical Design , 1996 .

[65]  Sarma B. K. Vrudhula,et al.  Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[66]  Carl Sechen,et al.  Chip-level area routing , 1998, ISPD '98.

[67]  Peter Widmayer On graphs preserving rectilinear shortest paths in the presence of obstacles , 1991, Ann. Oper. Res..

[68]  Jason Cong,et al.  VIA design rule consideration in multi-layer maze routing algorithms , 1999, ISPD '99.

[69]  Israel Koren,et al.  Optimal aspect ratios of building blocks in VLSI , 1988, DAC '88.

[70]  Roberto Tamassia,et al.  Dynamic algorithms in computational geometry , 1992, Proc. IEEE.

[71]  Alex Pothen,et al.  PARTITIONING SPARSE MATRICES WITH EIGENVECTORS OF GRAPHS* , 1990 .

[72]  Jason Cong,et al.  Large scale circuit partitioning with loose/stable net removal and signal flow based clustering , 1997, ICCAD 1997.

[73]  Jin-fuw Lee,et al.  An Algorithm for Incremental Timing Analysis , 1995, 32nd Design Automation Conference.

[74]  Majid Sarrafzadeh,et al.  On the behavior of congestion minimization during placement , 1999, ISPD '99.

[75]  Daniel Brand,et al.  Incremental synthesis , 1994, ICCAD '94.

[76]  David Eppstein,et al.  Sparsification—a technique for speeding up dynamic graph algorithms , 1997, JACM.

[77]  C. P. Ravikumar,et al.  A graph-theoretic approach for register file based synthesis , 1997, Proceedings Tenth International Conference on VLSI Design.

[78]  Jason Cong,et al.  DUNE: a multi-layer gridless routing system with wire planning , 2000, ISPD '00.

[79]  Jiri Soukup,et al.  Fast Maze Router , 1978, 15th Design Automation Conference.

[80]  David Eppstein,et al.  Sparsification-a technique for speeding up dynamic graph algorithms , 1992, Proceedings., 33rd Annual Symposium on Foundations of Computer Science.

[81]  J. Cong,et al.  Interconnect estimation and planning for deep submicron designs , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[82]  D. F. Wong,et al.  Simulated Annealing for VLSI Design , 1988 .

[83]  Oliver Chiu-sing Choy,et al.  Incremental layout placement modification algorithms , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[84]  E. Macii,et al.  High-level Power Modeling, Estimation, And Optimization , 1997, Proceedings of the 34th Design Automation Conference.