Process Variability Impact on the SET Response of FinFET Multi-level Design

Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability. These challenges can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power consumption. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The process variability is analyzed through the work-function fluctuations of the metal gate. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7 nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both ideal fabrication process and considering the process variability impact. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.

[1]  Massimo Alioto,et al.  Comparative soft error evaluation of layout cells in FinFET technology , 2014, Microelectron. Reliab..

[2]  E. G. Stassinopoulos,et al.  The space radiation environment for electronics , 1988, Proc. IEEE.

[3]  Karan Jasani,et al.  Realization of various error mitigation techniques for SRAM based FPGA , 2017, 2017 2nd International Conference for Convergence in Technology (I2CT).

[4]  J. Coffman,et al.  National Geophysical Data Center , 1985 .

[5]  Ulf Schlichtmann,et al.  Predicting future product performance: Modeling and evaluation of standard cells in FinFET technologies , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[6]  D. Munteanu,et al.  Modeling and Simulation of Single-Event Effects in Digital Devices and ICs , 2008, IEEE Transactions on Nuclear Science.

[7]  Richard Southwick,et al.  Total Ionizing Dose Radiation Effects on 14 nm FinFET and SOI UTBB Technologies , 2015, 2015 IEEE Radiation Effects Data Workshop (REDW).

[8]  Fernanda Gusmão de Lima Kastensmidt,et al.  Impact of different transistor arrangements on gate variability , 2018, Microelectron. Reliab..

[9]  Fernanda Gusmão de Lima Kastensmidt,et al.  Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology , 2017, Microelectron. Reliab..

[10]  Cristina Meinhardt.  Variabilidade em FinFETs , 2014 .

[11]  Jürgen Becker,et al.  Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors , 2014 .

[12]  L. W. Massengill,et al.  Single Event Transients in Digital CMOS—A Review , 2013, IEEE Transactions on Nuclear Science.

[13]  M. L. Alles,et al.  Multi-Cell Soft Errors at Advanced Technology Nodes , 2015, IEEE Transactions on Nuclear Science.

[14]  Ricardo Reis,et al.  Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements , 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[15]  Ricardo Reis,et al.  Radiation Effects on Embedded Systems , 2010 .

[16]  Sani R. Nassif,et al.  Process variability at the 65nm node and beyond , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[17]  K. Banerjee,et al.  Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design , 2010, IEEE Transactions on Electron Devices.

[18]  Samar K. Saha,et al.  Modeling Process Variability in Scaled CMOS Technology , 2010, IEEE Design & Test of Computers.

[19]  Tiago Roberto Balen.  Efeitos da radiação em dispositivos analógicos programáveis (FPAAs) e técnicas de proteção , 2010 .

[20]  peixiong zhao,et al.  Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes , 2010, IEEE Transactions on Nuclear Science.

[21]  R. Baumann.  The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction , 2002, Digest. International Electron Devices Meeting,.

[22]  Yi-Pin Fang,et al.  Neutron-Induced Charge Collection Simulation of Bulk FinFET SRAMs Compared With Conventional Planar SRAMs , 2011, IEEE Transactions on Device and Materials Reliability.

[23]  Ricardo Reis,et al.  Evaluation of SET under Process Variability on FinFET Multi-level Design , 2019, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC).

[24]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.

[25]  Christopher L. Henderson.  Failure analysis techniques for a 3D world , 2013, Microelectron. Reliab..

[26]  D. R. Ball,et al.  Geometry Dependence of Total-Dose Effects in Bulk FinFETs , 2014, IEEE Transactions on Nuclear Science.

[27]  R. D. Schrimpf,et al.  Modeling of radiation-induced single event transients in SOI FinFETS , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[28]  E. Simoen,et al.  Laser- and Heavy Ion-Induced Charge Collection in Bulk FinFETs , 2011, IEEE Transactions on Nuclear Science.

[29]  Saurabh Sinha,et al.  ASAP7: A 7-nm finFET predictive process design kit , 2016, Microelectron. J..

[30]  M.D. Berg,et al.  Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM , 2009, IEEE Transactions on Nuclear Science.

[31]  Rasit Onur Topaloglu.  Design with FinFETs: Design rules, patterns, and variability , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[32]  K. Endo,et al.  Variation analysis of TiN FinFETs , 2009, 2009 International Semiconductor Device Research Symposium.

[33]  Guillaume Hubert,et al.  Single-Event Transient Modeling in a 65-nm Bulk CMOS Technology Based on Multi-Physical Approach and Electrical Simulations , 2013, IEEE Transactions on Nuclear Science.

[34]  Massimo Alioto,et al.  Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[35]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[36]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[37]  R. Allmon,et al.  Soft Error Susceptibilities of 22 nm Tri-Gate Devices , 2012, IEEE Transactions on Nuclear Science.

[38]  Jean-Claude Boudenot.  Radiation Space Environment , 2007 .

[39]  Ravishankar K. Iyer,et al.  Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system , 1990 .

[40]  Cristina Meinhardt,et al.  Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations , 2014, Microelectron. Reliab..

[41]  Soonyoung Lee,et al.  Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices , 2015, 2015 IEEE International Reliability Physics Symposium.

[42]  T. Sajavaara,et al.  Linear Energy Transfer of Heavy Ions in Silicon , 2007, IEEE Transactions on Nuclear Science.

[43]  peixiong zhao,et al.  Muon-Induced Single Event Upsets in Deep-Submicron Technology , 2010, IEEE Transactions on Nuclear Science.

[44]  Dan Alexandrescu,et al.  Study of Neutron Soft Error Rate (SER) Sensitivity: Investigation of Upset Mechanisms by Comparative Simulation of FinFET and Planar MOSFET SRAMs , 2015, IEEE Transactions on Nuclear Science.

[45]  Asen Asenov,et al.  Intrinsic parameter fluctuations due to random grain orientations in high-κ gate stacks , 2006 .