Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.

[1]  R. Smoluchowski Anisotropy of the Electronic Work Function of Metals , 1941 .

[2]  Hongfa Luan,et al.  Dual-metal gate technology for deep-submicron CMOS transistors , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[3]  A. Sakai,et al.  Work function of binary alloys , 2001 .

[4]  V. Misra,et al.  Tunable work function dual metal gate technology for bulk and non-bulk CMOS , 2002, Digest. International Electron Devices Meeting,.

[5]  Yuan Taur,et al.  Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs , 2001 .

[6]  H. Michaelson The work function of the elements and its periodicity , 1977 .

[7]  Tsu-Jae King,et al.  Tunable work function molybdenum gate technology for FDSOI-CMOS , 2002, Digest. International Electron Devices Meeting,.

[8]  Carlton M. Osburn,et al.  Impact of gate workfunction on device performance at the 50 nm technology node , 2000 .

[9]  D. Frank,et al.  25 nm CMOS design considerations , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[10]  Chenming Hu,et al.  Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion , 2002, IEEE Electron Device Letters.

[11]  Bing-Yue Tsui,et al.  Wide range work function modulation of binary alloys for MOSFET application , 2003 .

[12]  Chenming Hu,et al.  Dual work function metal gate CMOS technology using metal interdiffusion , 2001, IEEE Electron Device Letters.