Partial scan: hardware and fault coverage trade-off

In this paper we present an efficient algorithm for the selection of flip-flops for partial scan design. The algorithm determines the vertex set to open loops of length K or higher. Applying the algorithm to several ISCAS-89 benchmarks yields the best results for large circuits. Our results consistently indicated it is sufficient to scan a smaller set of flip-flops than the MVFS without significant sacrifice in fault coverage. We have applied the algorithm to RTL benchmarks with promising results.

[1]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[2]  Sungju Park,et al.  A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination , 1992, Proceedings International Test Conference 1992.

[3]  Janak H. Patel,et al.  A fault oriented partial scan design approach , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[4]  Hugo De Man,et al.  Partial scan at the register-transfer level , 1993, Proceedings of IEEE International Test Conference - (ITC).

[5]  Irith Pomeranz,et al.  An optimal algorithm for cycle breaking in directed graphs , 1995, J. Electron. Test..

[6]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[7]  Sharad Malik,et al.  Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications , 1994, 31st Design Automation Conference.

[8]  Vishwani D. Agrawal,et al.  An economical scan design for sequential logic test generation , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[9]  Vishwani D. Agrawal,et al.  A Complete Solution to The Partial Scan Problem , 1987 .

[10]  Vishwani D. Agrawal,et al.  Pascant: a partial scan and test generation system , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[11]  V.D. Agrawal,et al.  Designing circuits with partial scan , 1988, IEEE Design & Test of Computers.

[12]  Jacob Savir,et al.  Good Controllability and Observability Do Not Guarantee Good Testability , 1983, IEEE Transactions on Computers.

[13]  Melvin A. Breuer,et al.  BALLAST: a methodology for partial scan design , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[14]  Pablo Sánchez,et al.  Partial scan high-level synthesis , 1996, Proceedings ED&TC European Design and Test Conference.

[15]  Alberto L. Sangiovanni-Vincentelli,et al.  An incomplete scan design approach to test generation for sequential machines , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[16]  S.M. Reddy,et al.  On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[17]  Miron Abramovici,et al.  A Cost-Based Approach to Partial Scan , 1993, 30th ACM/IEEE Design Automation Conference.

[18]  Vishwani D. Agrawal,et al.  An exact algorithm for selecting partial scan flip-flops , 1994, 31st Design Automation Conference.

[19]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[20]  Shang-E Tai,et al.  A three-stage partial scan design method using the sequential circuit flow graph , 1994, Proceedings of 7th International Conference on VLSI Design.

[21]  Rabindra K. Roy,et al.  The Best Flip-Flops to Scan , 1991, 1991, Proceedings. International Test Conference.