Phase Locked Loops Design and Analysis

New methods, for the design of dierent block diagrams of PLL, using the asymptotic analysis of high-frequency periodic oscillations, are suggested. The PLL description on three levels is made: 1) on the level of electronic realizations; 2) on the level of phase and frequency relations between inputs and outputs in block diagrams; 3) on the level of dierential and integro-dierenti al equations. On the base of such description, the block diagram of oating PLL for the elimination of clock skew and that of frequency synthesizer is proposed. The rigorous mathematical formulation of the Costas loop for the clock oscillators are rst obtained. The

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