High throughput architecture for high performance NoC

High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.

[1]  Eby G. Friedman,et al.  Sleep switch dual threshold Voltage domino logic with reduced standby leakage current , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Jong-Sun Kim,et al.  On-chip network based embedded core testing , 2004, IEEE International SOC Conference, 2004. Proceedings..

[3]  Hoi-Jun Yoo,et al.  An 800MHz star-connected on-chip network for application to systems on a chip , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[4]  Partha Pratim Pande,et al.  Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs , 2004, GLSVLSI '04.

[5]  Partha Pratim Pande,et al.  High-throughput switch-based interconnect for future SoCs , 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..

[6]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[7]  Eby G. Friedman,et al.  Optimum wire sizing of RLC interconnect with repeaters , 2003, GLSVLSI '03.

[8]  Muhammad M. Khellah,et al.  Power minimization of high-performance submicron CMOS circuits using a dual-Vdd dual-Vth (DVDV) approach , 1999, ISLPED '99.

[9]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[10]  Seung Eun Lee,et al.  Increasing the throughput of an adaptive router in network-on-chip (NoC) , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[11]  M. Elmasry,et al.  Power minimization of high-performance submicron CMOS circuits using a dual-V/sub dd/ dual-V/sub th/ (DVDV) approach , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[12]  Partha Pratim Pande,et al.  Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[13]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[14]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[15]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[16]  Partha Pratim Pande,et al.  Testing Network-on-Chip Communication Fabrics , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Hoi-Jun Yoo,et al.  Adaptive network-on-chip with wave-front train serialization scheme , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[18]  Partha Pratim Pande,et al.  A scalable communication-centric SoC interconnect architecture , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[19]  Russell Tessier,et al.  An architecture and compiler for scalable on-chip communication , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Luca Benini,et al.  Analysis of error recovery schemes for networks on chips , 2005, IEEE Design & Test of Computers.

[21]  Giovanni De Micheli,et al.  Design, synthesis, and test of networks on chips , 2005, IEEE Design & Test of Computers.

[22]  Mohammed Ismail,et al.  High throughput architecture for CLICHÉ Network on Chip , 2009, 2009 IEEE International SOC Conference (SOCC).

[23]  Timo D. Hämäläinen,et al.  On network-on-chip comparison , 2007 .

[24]  Argyrides Costas,et al.  Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) , 2007 .

[25]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[26]  André DeHon,et al.  Compact, multilayer layout for butterfly fat-tree , 2000, SPAA '00.

[27]  Hui-Fen Huang,et al.  Global interconnect width and spacing optimization for latency, bandwidth and power dissipation , 2005, IEEE Transactions on Electron Devices.

[28]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[29]  Eby G. Friedman,et al.  Optimum wire sizing of RLC interconnect with repeaters , 2004, Integr..

[30]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[31]  Partha Pratim Pande,et al.  Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.

[32]  Hoi-Jun Yoo,et al.  A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[33]  Radu Marculescu,et al.  Towards Open Network-on-Chip Benchmarks , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[34]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.