Inductorless oscillator design for personal communications devices-a 1.2 /spl mu/m CMOS process case study

Three different 1.2 /spl mu/m CMOS ring oscillator type VCO architectures have been presented. The VCO's are intended for the use as building blocks of digital radio frequency synthesizer. It is demonstrated that linear control and improved phase-noise performance can be obtained by employing circuit design techniques and time domain based circuit optimization. The measurements results indicate that the maximum oscillating frequency range from 460 MHz to 900 MHz, power dissipation (at 5 Volts) from 6.5 to 11.5 mW and phase-noise at a 100 kHz carrier offset in a range of -83 to -95 dBc.

[1]  Beomsup Kim,et al.  Analysis of timing jitter in CMOS ring oscillators , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[2]  T.A. Kwasniewski,et al.  A 1.2 /spl mu/m CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[3]  A. Abidi,et al.  Noise in relaxation oscillators , 1983 .

[4]  Asad A. Abidi,et al.  An all-CMOS architecture for a low-power frequency-hopped 900 MHz spread spectrum transceiver , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[5]  Qiuting Huang,et al.  1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 /spl mu/m CMOS prescalers , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.