Design and Implementation of 4x4 Vedic Multiplier using Cadence

Multipliers play an important role in today’s digital signal processing and various other applications. Multiplier acts as a key block element in high speed arithmetic logic units, microcomputer, image processing etc. Multiplication process basically requires more hardware resources and computation time than addition and sub-traction process. In the recent years growth of the portable electronic is forcing the designers to optimize the existing design for better performance. Vedic mathematics have sixteen sutras but “Urdhva-Triyagbhyam” is mainly used. Vedic method for multiplication which is different from the process of normal multiplication is presented. This paper proposes the design of Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. UrdhvaTriyagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. To enhance speed numerous modifications over the standard modified booth algorithm, Wallace tree methods for multiplier design have been made and several new techniques being worked upon. Amongst these Vedic multipliers based on Vedic mathematics are currently under focus.

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